Samsung announced recently that it started production of advanced NAND flash devices with 128Gbit, triple-level cell (TLC) NAND memory using 10-nm class process technology.
Similarly, Micron also announced in February that it would come to market with NAND flash devices with a memory capacity of 128 Gbit that also use TLC design. It was only last fall that Samsung introduced a 64 Gbit NAND flash using TLC and 21-nm process technology.
Clearly, the industry is moving toward TLC cell design even for demanding SSD applications. The concept of a multi-bit per cell technology was first introduced by Toshiba and for the last five years, all flash device makers have products using the 2-bit per cell design. (Download TechInsights' flash NAND technology roadmap here).
A multi-bit cell device has a high density and a low cost per bit, but usually has a reduced endurance. In a conventional single bit flash device the number of electrons placed on the floating gate affects the threshold voltage (Vt) of the cell. This effect is used to set the state of the cell to either high or low.
In a multi-bit cell the threshold is set to several different values. The difference in voltage between these levels is small, which puts an additional constraint of placing the charge precisely on the floating gate and of sensing it correctly. In a 2 bit per cell memory, the cell is put in four states. In a 3-bit per cell there are eight states (states = 2n), which imposes a colossal task for flash device manufactures to have a tight cell threshold voltage distribution and a precise sensing of cell data.
According to several papers, the number of electrons stored on a floating gate for the 30-nm node class is slightly less than 100. So, in a 21-nm node with the TLC design, the circuitry for placing and sensing charge on the floating gate is dealing with only a few tens of electrons in each state.
Therefore, Samsung’s 21-nm, 64 Gbit TLC NAND flash can be considered an industry milestone. It is the first commercial SSD product using the TLC design in 21 nm node. TechInsights has done a structural analysis of the 21-nm, 64 Gbit TLC NAND flash and is also following up with a waveform analysis.
The K9CFGY8U5A-CCK0 21-nm flash memory is one of the industry’s leading flash memory devices, packing 64G bits into a single 102.87 mm2 die, using conventional floating-gate flash memory technology. This NAND flash was found in Samsung’s latest SSD drive, the SSD840 (256GB). The basic teardown of the SSD drive is shown in figure 1.
There are so many definitions for efficiency, so cannot comment on your number of 70%
In any case, there is a strong possibility that the next 1X generation will be conventional floating gate with wrap around IPD and only after that 3D NAND will come.
It's a game of chicken among the four manufacturers. Who will go quadruple patterning with floating gate, and who will go 3D with charge-trapping. TLC is just to delay this fairly terrifying choice. It's a good topic for a betting pool.
“MLC to TLC is not doubling…”
What matters for the storage is Mbit/ unit area.
One method is to use Triple-Level- Cell and the other is to shrink the memory cell and have larger memory density. If error correction and stability can be guaranteed than TLC is a viable option for increasing the density. Of course the endurance is another topic.
Memory products have low margin of profit so using EUV is not the first option. In the future, NAND memory will go vertical and have 3D structures. 3D structures will have a relaxed pitch and the vertical integration will help increase the memory density.
It is an amazing achievement by itself when you look at the SEM picture of a 64 bits wordline and triple level per cell. I think we have a tendency to overlook and take for granted this kind of technology marvel.
Next step will be 3D with charge trapping cell where the channel is made out of poly. That will give a huge boost to the NAND density with a relaxed design rules
The processing of 8 or more cycles of device layers cannot be considered the same cost as a single cycle. There is multiplied material consumption as well as processing time. So this 3D cost-effectiveness thinking is self-deceit.
This point hits home when, in the SADP flow, the "spacer dep", "spacer etch" and "mandrel etch" were tagged as separate cost items in the cost stacks. If we applied this to 3D NAND specific process, we would have cost stacks 16 or 32 x higher!