This 21-nm NAND flash has abandoned the silicide process and opted for tungsten metal gate. This transition is not new; it has already been done in many DRAM products. However, depositing tungsten on poly is not a straightforward process; several interface treatments have to be done, which are described in the report.
Tungsten metal gates leads to controllable air gaps, which mitigate the parasitic capacitance. Other challenges including choosing a suitable inter-poly-dielectric (IPD) layer. The IPD thickness affects program/erase speed and magnitude of read current and the quality of the dielectric layers has a direct impact on the endurance of the flash device.
A thinner of IPD layer will increase the capacitive coupling between the control gate (CG) and the floating gate (FG) and generate a higher read current and a faster program erase mechanism but can also compromise the retention capability. So a tradeoff has to be made.
The IPD layer composition in 21-nm NAND flash is still the same as the previous generation but the individual layer thicknesses are modified. Also, in the Wordline direction, the aspect ratio for poly 2 gap-fill is greater than five. Here, too, Samsung has come up with new process techniques. Samsung’s 21-nm 64 Gbit TLC NAND flash technology has a process flow similar to its previous generation but with an enhanced process capability. It remains to be seen if the next generation 10-nm class 128-Gbits TLC NAND flash will manage to prolong the existing process flow or will take the next big step of fabricating 3-D NAND stacks.
Interested in NAND flash technology? You can check out TechInsights' technology roadmap for NAND flash here.
Arabinda Das is a senior process analyst at TechInsights.