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Samsung hits triple-level-cell NAND flash milestone

Tungsten metal gate.
5/1/2013 05:32 PM EDT
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resistion
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re: Samsung hits triple-level-cell NAND flash milestone
resistion   5/2/2013 12:42:32 PM
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75% area efficiency for 64 Gb at ~20 nm. Makes me think 3D NAND area efficiency degrades even further?

AD2010
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re: Samsung hits triple-level-cell NAND flash milestone
AD2010   5/2/2013 1:57:16 PM
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There are so many definitions for efficiency, so cannot comment on your number of 70% In any case, there is a strong possibility that the next 1X generation will be conventional floating gate with wrap around IPD and only after that 3D NAND will come.

KRS03
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re: Samsung hits triple-level-cell NAND flash milestone
KRS03   5/2/2013 5:30:42 PM
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Of course the concept goes back beyond Flash, there were multi-level EEPROM devices well over 10 years ago.

double-o-nothing
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re: Samsung hits triple-level-cell NAND flash milestone
double-o-nothing   5/5/2013 12:51:43 AM
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From MLC to TLC is not doubling of density they need something like 14 nm instead.

resistion
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re: Samsung hits triple-level-cell NAND flash milestone
resistion   5/6/2013 2:54:39 PM
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It's a game of chicken among the four manufacturers. Who will go quadruple patterning with floating gate, and who will go 3D with charge-trapping. TLC is just to delay this fairly terrifying choice. It's a good topic for a betting pool.

Diogenes53
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re: Samsung hits triple-level-cell NAND flash milestone
Diogenes53   5/5/2013 5:29:00 PM
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Still no sign of EUV on anyone's horizon. When will multi-multi-multi-patterning become so onerous as to force a cheaper alternative?

resistion
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re: Samsung hits triple-level-cell NAND flash milestone
resistion   5/6/2013 1:21:49 AM
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With MOSFETs requiring gate and gate oxide on sidewalls it is not likely there is enough room at ~10 nm hp or below.

AD2010
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re: Samsung hits triple-level-cell NAND flash milestone
AD2010   5/6/2013 2:19:34 PM
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“MLC to TLC is not doubling…” What matters for the storage is Mbit/ unit area. One method is to use Triple-Level- Cell and the other is to shrink the memory cell and have larger memory density. If error correction and stability can be guaranteed than TLC is a viable option for increasing the density. Of course the endurance is another topic.

AD2010
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re: Samsung hits triple-level-cell NAND flash milestone
AD2010   5/6/2013 2:22:30 PM
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Memory products have low margin of profit so using EUV is not the first option. In the future, NAND memory will go vertical and have 3D structures. 3D structures will have a relaxed pitch and the vertical integration will help increase the memory density.

beinglass
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re: Samsung hits triple-level-cell NAND flash milestone
beinglass   5/7/2013 10:50:20 PM
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It is an amazing achievement by itself when you look at the SEM picture of a 64 bits wordline and triple level per cell. I think we have a tendency to overlook and take for granted this kind of technology marvel. Next step will be 3D with charge trapping cell where the channel is made out of poly. That will give a huge boost to the NAND density with a relaxed design rules

resistion
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re: Samsung hits triple-level-cell NAND flash milestone
resistion   5/8/2013 12:50:41 AM
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The processing of 8 or more cycles of device layers cannot be considered the same cost as a single cycle. There is multiplied material consumption as well as processing time. So this 3D cost-effectiveness thinking is self-deceit.

resistion
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re: Samsung hits triple-level-cell NAND flash milestone
resistion   5/8/2013 5:54:47 AM
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This point hits home when, in the SADP flow, the "spacer dep", "spacer etch" and "mandrel etch" were tagged as separate cost items in the cost stacks. If we applied this to 3D NAND specific process, we would have cost stacks 16 or 32 x higher!

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