For its part, TSMC wants to use only EUV at 10 nm, patterning wafers just once, said Jack Chen, department manager for next-generation litho at TSMC. However, even if the approach works, TSMC may need to use a different technique at 7 nm and beyond that an upgraded EUV system with a finer numerical aperature (NA).
The design rules for 7 nm are still unclear and "if there is no high NA solution, EUV won't go beyond use at 7 nm," he said.
EUV has two top problems today. It lacks a strong enough power source to pattern about 200 wafers/hour required for commercial use. Also, masks for the approach still exhibit nagging defects.
Chen disclosed ASML has started a new working group to define a pellicle to cover EUV masks, shielding them from defects. It will be a requirement for commercial use of EUV, he told us.
ASML is working on a polysilicon membrane with Philips, its neighbor in Eindhoven, the Netherlands. Their prototype covers 80% of a wafer so far. "The next step is to turn the membrane into a full pellicle and find a commercial supplier to make it," said Chen.
Chen reported only minor progress on the long drive toward the Holy Grail of a 250W EUV power source. He showed data from a prototype system at TSMC in Taiwan using a new 10W source at a 20% duty cycle that it hopes to drive to 30W on a 100% duty cycle soon.
"We originally expected to show some higher power data to convince you EUV is coming, but unfortunately the tool is still down." Engineers had "a disaster with misalignment of the 200kW laser that damaged some other components," he said, noting the prototype system was back to life the morning of his talk.
The following pages offer a selection of slides on EUV that Chen and Phillips presented at the SPIE Lithography conference here.
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