For example, SRAM cells won’t get a full 50 percent shrink at 14 nm
without EUV, Ronse said. That’s because multiple patterning has some
limits in how closely it can place features.
“They can only catch
up if EUV becomes available,” Ronse said. “There [are] lot[s] of resources
going into development of light sources, so there is definitely a way to
get there, but it’s hard to estimate if it will be in two years,” he
Intel and TSMC recently committed billions of dollars to ASML (Eindhoven, Netherlands) which is developing the EUV systems.
also recently said it expects to make 14-nm chips next year and could
make 10-nm processors in 2015 using existing immersion lithography.
Without EUV, Intel believes it will have to write as many as five
immersion patterns on a chip which will take more time and money but is
IMEC now gets more than 60 percent of
production time with its ASML NXE 3100 EUV system installed here. “We
had quite some bumpy behavior in the first six months with average up
time declining from 50 to 10 percent,” due to problems with an older
light source, he said.
In its trials, IMEC has achieved device
resolution down to 16-nm half pitch with EUV. “EUV is most likely not
going to be used for all layers [in a chip], but for some critical
layers and will have to be aligned well for immersion,” said Ronse.
is also a problem. To date, IMEC has achieved alignment within 6 nm of
EUV and immersion layers on a chip. It needs to get down to alignment
within 2 to 3 nm, he said.
I strongly agree with your last statement and in fact the strongest value of integrated circuit is being integrated. Integrated function in one device instead of connecting many devices over PC board represent about an order of magnitude improvement in power performance and cost. An important differentiation to be made is between 3D IC using TSV vs. monolithic 3D. While the cost of devices using TSV is not lower but in fact higher the monolithic 3D IC provide cost reduction as we detailed in our Blog (http://www.monolithic3d.com/2/post/2012/06/is-the-cost-reduction-associated-with-scaling-over.html)
Just to clarify, Moore's Law was originally:
"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year... Certainly over the short term this rate can be expected to continue, if not to increase."
Stacking die can increase the number of components, but without any significant cost savings I'm aware of. That's not what Moore meant.
Moore's Law has been breaking down now for a decade, in that people like you and me, and practically every other engineer out there, no longer have any meaningful chance of developing a new state of the art chip in the latest process. Only a few remaining giant corporations can afford it, and they apply their fab technology to fewer and fewer high volume chips. The innovation that made Silicon Valley great is no longer being applied to the latest and greatest silicon. In 1988, I laughed at the 1.5 micron three-metal NMOS process used at HP, because everyone was on 1 micron CMOS by then. Anyone even one process node behind was literally a joke. Now days, there are many times more .35 micron tape outs than 28nm. I'm sorry, but Moore's Law is a corpse that is just still twitching...
EUV, unless some fundamental breakthroughs magically appear, will not save Moore's Law.
That said, 3D stacking is cool, and I hope it works out as you envision. There is enormous value in being smaller, if not cheaper.
Yes, I agree. Moore's Law is on going and if you look to the original Moore forecast (1965) it is about: " the number of transistors on integrated circuits doubles approximately every two years". Moore attribute it to three trends: Decrease dimension, larger die and improving the architecture. Monolithic 3D is part of the last two. We wrote more about in in our Blog (http://www.monolithic3d.com/2/post/2011/03/guest-contribution-entanglement-squared-by-zvi-or-bach.html)
Isn't monolithic 3D really just an area bump, with some plusses and some minuses? You could in principle also just make chips physically larger in 2-D. A 3-D chip with 2 physical layers is not easier to make than double patterning 1 physical layers, is it? Seems quite similar to a multichip module. My impression is most applications are after higher nodes not because they desperately need more than 10 billion transistors, but that they need better device parameters or cost per transistor.
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