The through-chip interface (TCI) compares favorably with today's wired through-silicon vias (TSVs) and traditional chip-to-chip links such as low-power, double-data-rate memory (LPDDR), says the startup.
1. Yes, it is appealing to demo wirelessly sending power as well as signals. This has been demonstrated in several published papers already, but works best when the power consumption is very low. For many cases, simple wire bonding for power/ground is sufficiently good and low cost that you would have to very carefully examine the tradeoffs to determine when to use wireless power distribution vs wired.
2. According to professor Kuroda, resistive and reactive losses are not big effects. Even using what is normally highly resistive metal0 available in some processes seems to work fine. Bigger issue with bandwidth is simply the quality of tranistor, which is better in high speed digital processes and not as good in processes for DRAM or NAND FLASH.
3. Yes, conventional thickness silicon can be supported, so long as the diameter of the coils is about 3x the distance to be travelled wirelessly. But anyone serious about 3D stacking would probably use die thinning, which can result in die an order of magnitude thinner die than standard wafer thickness. See the slide titled "Range Extended by Enlarging Coil Size" and you can trade off coil size with distance and bandwidth.
4. You can put many channels in parallel, or use a Ser/Des to reduce the number of channels between die.
Regarding the queston: "Can someone explain how 3-D stacking saves money, because the silicon die cost remains the same?" Your assumption about "silicon die cost reamains the same" is incorrect for some stacking approaches. Thru Silicon Vias (TSV) offer nice improvements in reducing power compared to wire-bond, for example, but it requires a non-standard CMOS process that can cost substantially more, so die costs for TSV do not reamain the same. TSV is also hard to rework yield defects, which further increases costs. All of these challenges to build TSV combine to increase costs compared to the original non-TSV die typically by 1.4x to 2x. Ask your fab for actual costs for TSV. This often makes the TSV approach too expensive compared to the technical benefit. By using ThruChip's near-field inductive coupling approach to data communication between stacked chips, the die costs could essentially remain the same, as no new semiconductor process is required. With the ThruChip stacking approach, similar benefits to TSV can be achieved without die cost increase. Reductions in I/O circuitry and lower power with ThruChip could lead to cost reductiions as well. -- ThruChip CEO Dave
There should not be any difficulty in "manufacturing of the coils" as the thruchip coils are made from normal wires. Don't think "wireless" as in radio, instead realize that this is just simple near-field inductive coupling. All designers have to worry about coupling between wires on their chips, but in this case professor Kuroda realized that by making a few simple turns of a standard wire, with diameter about 3x the distance to be travelled, that the coupling was so strong that it could be made as reliable as a wired connection. As you can see in the diagram, the circuits driving and receiving from the coils are relatively simple digital circuits, and will scale with future technology scaling as long as Moore's law continues. As there are no special CMOS process change required, in many cases there would be no increase to the cost of each die, which is not the case with other technologies like TSV. Completely agree with your point that this would act like an accelerator to Moore's law, allowing N times the number of transistors to be placed in the same area when stacking N chips. -- ThruChip CEO Dave
As replies in my earlier comment, it will not require a SerDes as it purely creates a Digital Coupling Link, serialization is not essentially required. But SSN and Signal Integrity will be a major issue near and needs detailed study, I think there will be surely some papers describing details of it, also the article says that there is an example of thousand such link on a single chip so it will be discussing about SSN and Signal Integrity in detail.
@chipmonk0: On page two of this article, there is a table comparing these two technologies TSV vs TCI, which also mentions about the number of channels, area/channel and data rate. Does this help to answer your questions to some extent? I understand the communication would be using serial channels (Tx/Rx). Not sure about the pros/cons of increased speed upto >5Gbps though.
It would be a far more appealing demo to have the power signals, not just data, transmitted wirelessly. There might even be an energy harvesting opportunity here. Other questions still need to be answered as well. Do resistive or reactive losses in the coils limit the bandwidth? Do the wireless links allow conventional thickness silicon? What are the multiplexing options?