For example, SRAM cells won’t get a full 50 percent shrink at 14 nm
without EUV, Ronse said. That’s because multiple patterning has some
limits in how closely it can place features.
“They can only catch
up if EUV becomes available,” Ronse said. “There [are] lot[s] of resources
going into development of light sources, so there is definitely a way to
get there, but it’s hard to estimate if it will be in two years,” he
Intel and TSMC recently committed billions of dollars to ASML (Eindhoven, Netherlands) which is developing the EUV systems.
also recently said it expects to make 14-nm chips next year and could
make 10-nm processors in 2015 using existing immersion lithography.
Without EUV, Intel believes it will have to write as many as five
immersion patterns on a chip which will take more time and money but is
IMEC now gets more than 60 percent of
production time with its ASML NXE 3100 EUV system installed here. “We
had quite some bumpy behavior in the first six months with average up
time declining from 50 to 10 percent,” due to problems with an older
light source, he said.
In its trials, IMEC has achieved device
resolution down to 16-nm half pitch with EUV. “EUV is most likely not
going to be used for all layers [in a chip], but for some critical
layers and will have to be aligned well for immersion,” said Ronse.
is also a problem. To date, IMEC has achieved alignment within 6 nm of
EUV and immersion layers on a chip. It needs to get down to alignment
within 2 to 3 nm, he said.
would it not be better to make a larger step and go to directed self-assembly (DSA)? multi-patterning feels very incremental with some gains due to smaller feature size and some losses due to lower throughput
The EDA enablement of multi-patterning provides a path to maintain a path along Moore's law. The only hesitation has been cost. But what most people are ignoring is the fact that by the time they get an EUV system capable of the numbers they need it will probably cost more than multi-patterning with traditional steppers, and it may even need multi-patterning itself.
"Without EUV, Intel believes it will have to write as many as five immersion patterns on a chip which will take more time and money but is still economical." Hope it is true. But when litho rework rate boomed with strigent process requirements in triple and above patterning, process window and yield are impaced severely. It will be hard to see economic advantages in dimension shrinking. It is happening in current 22/20nm processes(double pattern) and getting worse for 14nm and beyond. That is the reason why Intel/Samsung/TSMC(even nVidia) are urging 450mm progress in parallel to lower down process cost. Tons of hurdles ahead, Go engineers.
Wow, that's quite a while back, if I read those papers, maybe I would have reconsidered joining this field, who knows ;-)
I guess saying scaling won't happen would be much riskier than saying a particular way of scaling won't happen.
This has been known for years @resistion...I attended IEDM conference 20 years ago where this issue was discussed ;-)...talks about slowing of the Murphy's law started shortly after "the law" was established...I remember limits at 1 micron level considered insurmountable ;-)...but it might be true this time around...litho is clearly a huge challenge...but not the only one...Kris
Something they should have known. So much more energy absorbed from a shorter wavelength photon into a smaller space, obviously higher energy density needs to be dissipated into a larger volume to avoid unwanted material changes.
In one form or another, multiple patterning becomes necessary.
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