Latest project: NetComposer-1 structured ASIC platform, built with a 0.13-micron process. Contains 1 million gates of logic for the NetComposer body and 2 million gates for the metal programmable cell array. The CPU core runs up to 500 MHz; the system speed is 150 MHz.

Design team: About 40 people

Design tools: Synopsys synthesis suite, Cadence NC-Verilog simulator, Synplicity Synplify-Pro, Xilinx ISE, Novas/SpringSoft debugger

Faraday's most ambitious project is a platform-oriented structured ASIC called NetComposer-1 (NC-1). It was the company's first product to tackle high-level networking, in Layers 4 through 7. It incorporated highly integrated, system-level IP, ranging from the CPU and memory controllers to I/Os, but left blocks open for customer IP.

"The methodology and the design flow are different," said Irving Liu, architect and product line leader. "We needed to find a model for co-development with the customer, from simulation, emulation and verification. We want to provide the best quality of service from the system level, not just the individ-ual IP."

That in itself is another challenge. How far should the company go to offer support? Go too far and the general-purpose platform becomes overly specialized, taxing the engineering resources.

"We want to provide uniform but minimum overhead when we do the service. Some customers will try to drive us to provide all that they want, but that may exceed what we can do," Liu said.

So far, Faraday's early customers are using NC-1 in very different areas, including network security applications, such as IPSec VPN or content inspection, using the NC-1 as a security gateway or security NIC. The NC-1 has also been applied as a system-on-chip platform for flow-through-based design for networking storage, iSCSI applications or as a remote DMA engine for TCP off-load.