A design services firm launched as a joint venture between STMicroelectronics and Cadence Design Systems

Latest project: A 300k-gate, 0.13-micron IC for gaming in the consumer market, targeting high production volumes and requiring an aggressive design schedule, including parallel software, firmware and pc-board development

Design team: 25 hardware and software engineers

Design tools: Cadence tools are used for functional verification and silicon implementation, Synopsys for synthesis and timing verification, Mentor Graphics for automatic test pattern generation, Synplicity for FPGA prototyping and Xilinx's development environment for FPGAs.

Plenty of challenges confront EDA tools at current process nodes of 90 nm and up, said Alessandro Uguzzoni, project leader for physical design at Accent SRL. They include achieving accurate characterization for physical libraries for an adequate set of operating conditions and tools; guaranteeing the quality of final results at the start of the project, with limited insights about final changes to design; and maintaining consistency of timing information among tools.

"Power consumption in UDSM [ultradeep-submicron] processes will be an especially big challenge," Uguzzoni said. "Aggressive solutions at the physical level are being proposed from EDA, foundry and library providers, but integration in a seamless flow will require more time. In any case, this will increase significantly the physical-design time, thus increasing NRE [nonrecurring engineering] costs."

Also a problem are the multiple operating conditions EDA tools must address simultaneously, at least for timing and electrical rule check signoff.

As technology nodes become more advanced, the designs become more complex and the number of corner cases to optimize for and to verify is likely to explode, Uguzzoni said. Such complexity, he said, will require considerable investments in engineering skill and specialized EDA software.

Uguzzoni urges: