ASIC Issues

Custom Integrated Circuits Conference New technologies and techniques being developed to improve circuit and system performance were the subject at the Custom Integrated Circuits Conference. by R.T. "Tets" Maniwa

The seventeenth annual Custom Integrated Circuits Conference (CICC) was held in Santa Clara, CA, on May 1-4. CICC continues to provide an international forum for academic and industrial researchers and technologists to describe recent advances in technology. The ability to develop new circuit techniques and topologies to improve performance is one of the keys to continuous increases in integrated circuit complexity and performance.

The keynote address by James Carnes, president and CEO of the David Sarnoff Research Center (Princeton, NJ), was titled "The Convergence of Computers, Communications, and Consumer Electronics." In his speech, Carnes presented insights and predictions of the unfolding multi-billion-dollar markets. The driving trends of time-to-market and increased functionality per dollar are requiring ever more powerful computers to operate with other networked resources for the same or lower costs every year.

The educational sessions were well attended. It was standing-room-only at the high-performance design session, which consisted of speakers who described various aspects of design optimization for higher performance and lower power, and showed that these two parameters may not be mutually exclusive.

Bijan Davari, of the IBM T.J. Watson Research Center (Yorktown Heights, NY), covered CMOS technology for low-power, high-performance design with an emphasis on the tradeoffs and optimizations that can enable increased density, improve performance, and reduce power all at the same time. The main idea was to consider the power supply voltage as another variable in the device parameter equation. This allows the designer to optimize device structures for speed (a function of size and voltage) and power (a function of operating frequency and voltage) without jeopardizing the reliability or packing densities. Two examples of scaling dimensions and operating voltages showed the potential for large increases in packing density without corresponding increases in power consumption.

Anantha Chandrakasen of the Massachussetts Institute of Technology (Boston, MA) presented the second topic of design methodologies for low-power digital systems where a combination of architecture optimization and voltage scaling allows tradeoff between silicon area and low-power operation. The talk made particular emphasis on the need for systems to process data to achieve some desired throughput and no more. Such systems encourage a design methodology emphasizing internal architectures with maximal parallelism and minimal pipeline lengths. Chandrakasen noted that a general purpose microprocessor has an extremely bad architecture for low power, since most microprocessors are waiting for up to 98 percent of their cycles for some inputs. He suggested a dynamic threshold adjustment in circuits to minimize power consumption in unused sections of the IC.

A signal on a back gate contact can reduce the threshold voltages by increasing the depletion region in the conduction channel and reduce leakage and static operating currents in non-operating portions of the IC.

Bob Cordell of Bellcore (Red Bank, NJ) gave the third address, speaking on clock generation and distribution. He discussed multiphase and multiple clock frequencies on a single chip and the issues associated with complex clocking. As clock frequencies increase, clock integrity becomes more of an issue.

Parasitic elements of the interconnections, propagation delays in the logic, and the overall size and speed cause clock skew and clock signal integrity problems. At the same time, the higher speeds and associated higher currents in the wires can create thermal and reliability problems. Using phase-locked loops (PLL) for on-chip clock generation and clock edge de-skewing is one solution, especially for sub-multiple or frequency multiplied clocks. Cordell discussed some implementations of phase, and phase-frequency detectors and a number of voltage controlled oscillators, all elements for PLL functions.

The other educational sessions covered analog and wireless design, and communication technologies. These sessions presented basics of RF design, digital wireless systems, micropower analog CMOS, and bipolar analog design techniques. These tutorials provided working descriptions of the design requirements within the individual topics, with emphasis on the basic techniques and general subject material.

The presentation by Michael Adams of Time Warner Cable (Englewood, CO) described the convergence of computers, communications and consumer products in a set-top box for interactive networks. Time Warner is a network operator, so the set-top does not drive the system, but they need to have a network architecture which allows the set top to fit in. The network must start from the concept that the system must support the analog services, all of the pay per view, premium channels and the old analog channels, plus electronic program guides. New set-top boxes need to add in the digital broadcasts and digital interactive services.

Time Warner added digital functions to the existing analog box by installing a high performance CPU, graphics card, and 8 Mbytes of RAM. This is not the way to get to a $300 box and they are transforming the basic design to a lower cost version. The costs are being reduced by integrating more into silicon. The $30/Mbyte prices are not dropping as fast as desired, so they are working on reducing the size of the applications and using more library functions to reduce total memory, get higher through-put, and reduce the loading on the network. In addition, they are looking at new memory architectures like RamBus shared memory for better memory utilization.

The result of the trials in Orlando, FL, is a network that allows viewers to call up what they want to see on an interactive basis. For things like news, the viewer can get as much detail as desired on any story, much like an interactive encyclopedia. They have achieved a state where each person has individual control of the programming and a virtual network for one person.

The luncheon presentation featured Frank Cepollina of the NASA Goddard Space Flight Center (Huntsville, AL) who spoke on the Hubble Space Telescope (HST) and the space shuttle repair mission to fix the errors in the optics, as well as the future changes and upgrades to the HST. Started in 1972, the design modular for the HST has replaceable component subsystems, The final system was launched in 1990 to great expectations for optical performance in the astronomy and astrophysics groups. The actual performance led to disappointment when an optical flaw (due to an error in grinding and polishing amounting to 2.5µm across the 2.4-meter main objective diameter) caused optical aberrations. NASA developed software models of the components, performed extensive simulations, built hardware models and tested them in a prototype (including prototyping the installation and calibration procedures), and finally installed the components into the HST system. The results now meet the expectations for the astronomy and astrophysics communities and are helping to push our understanding of the universe.

One of the direct benefits of the technologies developed for the HST is the improved ability to design and produce very high grade optics. The correction optics had a surface smoothness of less than three angstroms. The ability to measure and produce the very high precision surfaces such as those in the correction optics in the HST will have an effect on the IC industry. This lens polishing capability will show up in the next generation of optical lithography equipment and will enable lower diffraction lenses, which will be used to image the features in the next generation silicon processes.

The shorter sessions for the regular papers included topics that address the types of circuits enabling the converging trends of computers, communications, and consumer products. These papers were organized into 28 sessions, with a relatively even mix of academic and industry papers, covering topics including digital, analog, and mixed-signal circuits with applications in audio, video, computers, and communications. Many of the topics showed up in a number of different sessions, consistent with the general theme of converging trends and technologies.

Some of the presentations referred to the need to add steps in the design flow to address the complexity, testing, and reliability issues while allowing more time within the various design and analysis iterations before going to the vendor. The designer is distracted by issues of modeling and library development (in addition to the intricacies to include non-digital subsystems in a high performance chip) from the job at hand, namely the development of new systems to reach the market during the open window period. The increases in analysis cause the design to go through more loops, but improve the probability of success when finally going to a silicon vendor for an ASIC.

The many topics on circuit design addressed specific instances of adapting a technology and a design topology to achieve a higher performance and/or lower power circuit. Even these impressive results, however, belie the nature of the custom work, since the general level of custom circuits seems to lag behind the full potential of the silicon, as evidenced by the differences in performance of the highly optimized full custom ICs and more general custom parts. The DEC alpha chip clocks at 300 MHz, while most ASICs struggle to achieve 100 MHz. The difficulty is in simultaneously achieving the schedule, performance, power, and cost targets for a high complexity circuit. The EDA tool vendors are now working on the deep submicron tools that will interconnect the design, floorplan, extraction, analysis, and synthesis cycles necessary for the very large chips.

The sophistication and capabilities of the design tools seems to lag behind the potential available in silicon. Part of the difficulty seems in getting the users to understand the new models and the effects of the design methodology changes. The new methodologies for the very large ICs will require technologies which allow the whole engineering team to work together simultaneously on the different pieces of the chip. If, indeed, the converging trends of computers, communications, and consumer products continues, the next generation of ASICs will have multimedia capabilities, implying on-chip circuitry to handle logic, video and audio, and communications. The design complexity will require design and applications expertise in MPEG video, audio, and network systems all coming together in a small, lightweight, low-cost system-on-a-chip which has high reliability, ease of use, and may even be a wireless system. This combination of applications may be much more challenging for the tools and for the designers than any of the current designs.

The techniques and methodologies described at CICC will help designers to optimize various subsections within the next generation of integrated circuits. Somehow the rest of the tools and applied creativity in the design community will find some way to use all that silicon performance. As Frank Cepollina said in his speech, "Thanks to all of you for the technical expertise and technical developments which made possible the developments and upgrades of the Hubble Space Telescope. You have provided orders of magnitude improvement in the research capabilities in the areas of astronomy and astrophysics."

Tets Maniwa is the technical editor for Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  August 1995