ASIC Issues

Extra Silicon Is Free The cost of an extra gate is not the same as its value. by R.T. "Tets" Maniwa

The thought of getting something for nothing appeals to all of us. With the advent of very large, deep submicron custom products, we are now approaching a point where incremental gates are free. The latest announcements from Hitachi (Brisbane, CA) and VLSI Technology (San Jose, CA) of 0.35µ, five million gate arrays confirms the SIA projections of ever-increasing chip complexity and of decreasing costs, approaching microcents per gate by 2010. In spite of this asymptotic approach to zero gate cost, ASICs should not be evaluated on a cost-per-gate basis.

Designers need to consider measurements other than millicent per gate for appropriate pricing. The cost per gate for a 100 kgate device in a three-layer metal process would be lower than the same size array in a five-layer metal process, but the five-layer part has almost twice as many routable gates as the three-layer part. Cost-per-gate analysis ignores many other facets of total product cost, such as packaging and testing. A low-priced IC may not have adequate testing, appropriate delivery schedules, or an extensive set of tools and libraries that can reduce the total design time. The existence of these types of attributes may be enough to affect the total development time and expedite the time to market.

The industry trends towards more functions for the same dollars, or the same functions for fewer dollars, drives us to get more into a single chip. The IC vendors have responded by developing products and processes capable of including over a million gates in a single IC. Recently Hitachi and LSI Logic announced a gare array family with up to five million gates. Brian Matas, senior analyst at Integrated Circuit Engineering (Scottsdale, AZ) noted "This validates the 0.35µ technologies as the ASIC technologies of choice. In the past, the DRAM process technology was the overall process driver, but ASIC technologies are becoming just as important,and may be just as important a technology driver for those companies doing well in ASICs. The ASIC vendors may start using the ASIC technologies and methodologies for mainstream products."

This geometric increase in device complexity and levels of integration propels two divergent trends in ASIC costs. The smaller feature sizes enable many more gates per unit area, reducing the effective cost per gate. At the same time, the smaller features give rise to higher manufacturing complexity, which increases the costs per wafer. Although the die area per function is dropping as a square function while the wafer processing costs are relatively linear per additional layer, the overhead costs for the fab are starting to dominate the total die cost. The latest wafer fabs are expected to cost over $1 billion for a facility that would be useful for "state of the art" production for only about two years. As we continue to ask our ASIC vendors to reduce the prices for their products, we demand more from their technologies. We continue to ignore the basic economics of the industry at the risk of long-term vendor viability.

In order to appreciate the distinctions of gate cost versus gate value, we must evaluate the basic model for total product utility and determine the additional value for any incremental gates. The primary basis for determining the cost of an ASIC is the die area, or active die area for some evaluations. The active area measurement takes into account the parameters of defect density and relative open space on the chip. The industry and academia have developed a number of different models for defect density, from overall composite defects per area, to average defects per layer, to accounting for the varying impact of defects on different layers. For example, a defect on an isolation layer or a via is much less important to the overall device performance than one on a gate implant or first metal.

Figure 1. The estimated net die per wafer based on a Murphy model that estimates yield as a function of die area and composite defects per square millimeter. Assumes two defects/mm 2 .

Extra value gates An example of the value of extra gates is the addition of internal self-testing capabilites to a part, which may add additional thousands of gates to the design. If the design is a 500 kgate design being placed in a one-million gate array, the additional 10 kgates for BIST are already included on the die and are available in the basic part. The additional gates may even reduce the total cost of a part if the incremental gates are used to improve testability or internal visibility. The inclusion of a few more functions may eliminate some external components, reduce the package pin count, and reduce the total assembly and manufacturing costs. A smaller set of test vectors is more likely to fit within the limitations of the existing test systems. Therefore, the addition of a number of additional gates may even be considered a cost-reduction feature. At this high level of analysis, the use of additional gates is worth the design time since the additional gates do not really cost anything per IC and the added functionality adds great value and reduces other manufacturing costs. In this case, the fixed unit cost of the gates is way out of proportion to the increased value of the additional gates.

In general, analysis of gate utility and value shows increased value per incremental gate. This remains true until you exceed the available I/O pins or the capacity of the routing resources. The usual limits for usable gates range from about 40 percent of the total available gates for a dual-layer metal part up to about 75 percent for a five layer device. The limits for pins are a function of the die size and final packaging. ASIC vendors tend to dislike designs that push the definitions of practical limits since a larger design implies greater complexity, more extensive testing, and lower yields. Submicron designs are more susceptible to faults and defects since they have feature sizes in the same order of magnitude as the defects and the particles that can cause faults in the features on the silicon.

The problems that arise when the design exceeds available resources, like area for routing or I/O pads, can be horrendous. A best-case resolution is to move to the next larger array and cut and paste the old layout into the new array. This solution obviously doesn't work if you are already in the largest array in the family. The additional costs for the larger array include the increased NRE plus the higher unit price plus the costs for the delays in finishing the design and layout. The step function for the pricing of the different sizes of arrays reflects the expected yield. Figure 1 shows an estimated yield for various die sizes, based on a Moore model, using a composite defect density of 1/cm ² on 200mm wafers.

For high-volume production, quantities of greater than 100k units per year, an alternative to the next larger gate array is a full custom part, in either a standard cell or full custom implementation. The number of units can justify the $250k+ NREs for a full custom part that could be as little as half of the size and less than half of the cost of an array-based design. The major tradeoffs in this case are the inability to observe working silicon until after the first parts come out and time to market, due to longer design times and wafer fabrication cycles. For the smaller volumes, the full custom approach is probably not viable. The extra costs for the NRE over a two-year product lifetime can add the equivalent of over $10 to the unit cost of the IC. Here the effective cost of an additional gate is much higher than would normally be expected. Even though a full custom gate is usually smaller than a gate in a gate array or standard cell, and therefore expected to cost less, the additional gates are extremely expensive.

Another potential added cost for extra gates is the packaging. The smaller gate-count part may be able to fit into an inexpensive package, while the larger part might need to be placed into a complicated, expensive package with special thermal characteristics to handle the extra power consumption. If the additional gates require a package with more pins, the package outline may change, and the PC board may require more layers to handle the interconnect density. These costs are not directly measurable in the design stages, but are important in understanding the "hidden" costs of incremental gates in a design.

The cost of a gate is a single-point metric that can be considered in evaluating ASIC vendors, but not as an isolated quantity with no interaction with the other significant measurements associated with product costs.

Tets Maniwa is a technical editor for Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  September 1995