ASIC Technology

Foundry Portable Designs

With foundry capacity continuing to be at a premium, the ability to switch designs from one foundry to another could prove to be the solution to designers threatened by limited capacity.

by Brian Henderson, Rakesh Kumar, Riko Radojcic, and Minh Bui

Within the last decade the semiconductor industry has experienced a major transition in the way it produces integrated circuits (ICs). Traditional vertically integrated manufacturing has given way to distributed methods such as with application-specific integrated circuits (ASICs) and customer-own tooling (COT), where much of the physical design implementation and wafer fabrication/production flow is outsourced.

The driver for the fabless trend lies in the escalating cost of in-house silicon production. The capital cost of a ground up, competitive CMOS manufacturing facility has increased some 10 times in 10 years, and today costs on the order of $500 million to $1 billion. Clearly, such costs are prohibitive for all but the largest semiconductor suppliers and therefore most design houses opt to be fabless.

The demand for silicon foundry services is increasing at approximately 35 percent annually, the result of both the increase in the pool of fabless companies and also from the growth in demand for all IC product families including chip sets. Consequently, the industry today is experiencing a shortfall in foundry capacity that is expected to persist through the end of the decade. Surplus capacity at 0.8µm or less is now at only three percent, according to VLSI Research.

Given that foundry capacity will remain at a premium, one solution lies in the ability of design houses to switch their designs between foundries as capacity is threatened. Second-sourcing done rapidly protects the revenue stream and profitability. For new design work, opportunities include the use of foundry portable libraries, as provided by Compass Design Automation (San Jose, CA) for example, or the utilization of foundry "common" design rules that are compatible between foundries. For many with completed designs or with design complexity not supported by commercial libraries, however, porting between foundries is more difficult. The purpose of this article is to describe porting options and to outline the relative merits, methods and our experiences in performing a GDSII, "physical" port between foundries. GDSII is an industry-standard geometric description of the chip design suitable for mask making.

Porting options Transferring existing designs between silicon foundries can be achieved in several ways as follows, each with its own cost and time-to-market implications.

Recapture: redesign using new netlist, library, models, foundry

Netlist port: redesign with existing netlist, new library, models, foundry

Physical port: uses existing physical design, GDSII data adjusted for foundry

Technology port: transfer wafer process to foundry, uses existing physical design

Figure 1 has a summary description of each approach along with the relative merits. With the recapture approach, the designer must entirely respin the design using the tools, library, and timing models compatible with the new foundry. While this is a valid option, it tends to be expensive in terms of design resources (a fact especially felt in small design companies), costing $50,000-$100,000 plus foundry NRE, and incurring the full redesign period of four to six months for first silicon. The advantages are that the finished product is optimized against the foundry technology and that timing and functionality are verifiable with the design tools. Further, one may take advantage of any technology improvements that are available, such as an added layer of metal, etc.

The second option, eliminating the need to recapture, is to port the design at the netlist level. That is, no attempt is made to modify the original netlist based on a new library. For this to work it requires that equivalent library elements and naming conventions exist between the original and foundry libraries. Due to library element requirements this may only be realistic using an ASIC approach or a provided third-party library. The modified chip will have the same library elements as the original, but the design place and route may be optimized differently. It also requires that the original and foundry technologies are closely matched to be confident of performance equivalence. The advantage of this approach is that logic capture and synthesis are eliminated, thus reducing the design cycle time.

Figure 1. Comparison of the physical port method for exising designs against the alternatives. The physical port approach offers low design cost and fastest time to first silicon.

The third option is to execute a port at the physical or GDSII level. With this approach, all physical features of the design including cells, placement, routing, floorplan, and interconnect are identical between the original design and the new design for the foundry. To ensure foundry compatibility, the physical GDSII layers are manipulated, sized, and otherwise adjusted to meet design rule and performance requirements.

Since recapture, netlist, timing verification, and place and routing operations are eliminated this method clearly has the potential for optimal time to market. With a pure physical port there is, however, inherent risk of not being able to meet all foundry layout and reliability rules and/or functionality or performance requirements of the design. In other words, since the original design was optimized around a library and models assuming a given technology, a shift to a different technology is a major deviation and needs careful attention to meet design goals, manage risks, and make the port successful. While many technical differences between one technology and another seem likely to foil the attempt, our experience shows that many of the obstacles may be overcome, making the physical port possible.

Table 1
Foundry selection spreadsheet -- technology exerpt
Technology	Weighting (w)	Design Requirement	Foundry Technology	Compatibility Factor (c)	c*w
Maximum die size (mm)	1.3	15	17.5	1	1.3
# interconnect layers	1.3	3	3	1	1.3
Power supply	1.3	5 +/- 0.5	5 +/- 0.5	1	1.3
Buried contact	1.3	No	No	1	1.3
Substrate type	1.3	P/P+	P- or P/P+	1	1.3
Silicide poly	1.0	No	TiSi2	0.5	0.5
Silicide junctions	1.0	No	TiSi2	0.5	0.5
Gate ox thickness (A)	1.0	160	150	1	1.0
Leff N (nom)	1.0	0.75	0.70	1	1.0
Leff P (nom)	1.0	0.75	0.70	1	1.0
Idsat/um n-ch (nom)	1.0	0.39	0.44	1	1.0
Idsat/um p-ch (nom)	1.0	0.18	0.20	1	1.0
Vt n-ch (nom)	0.7	-0.75	0.70	0.75	0.5
Vt p-ch (nom)	0.7	-0.85	-0.85	1	0.7
Poly sheet (ohms/sq)	0.7	40	<5.0	0.5	0.3
N+ sheet (ohms/sq)	0.7	65	< 5.0	0.5	0.3
P+ sheet (ohms/sq)	0.7	110	< 5.0	0.5	0.3
Average	1			Index = 0.87

For completeness, the fourth option is a physical port variation where the original manufacturing technology is transferred to the foundry. This makes the design port very straightforward, requiring perhaps just an adjustment to masks to compensate for wafer process equipment differences; however, since installation of a new process flow is expensive, most foundries are unlikely to agree to this unless there is a significant business opportunity.

Physical port: phased approach

* Foundry technology identification

* Definition of GDSII porting algorithms

* Critical path simulation

* Identification of main design rule and technology issues

Technology screening As one would expect, an initial screening of technologies must be made against the existing product requirements. An extract of a spreadsheet comparison for technology factors is shown in Tables 1 and 2. A similar format to look at layout design rules, reliability factors, transistor and interconnect performance, etc., is also necessary. The data shown is representative of a triple-layer metal, submicron CMOS physical port test case undertaken at Unisys.

In a spreadsheet form one may easily compare several technologies and assign a compatibility index number. As shown, each parameter being compared is assigned a weighting factor (w) corresponding to importance in performing the port. For example, the number of interconnect layers of the foundry technology must be weighted highly and would obviously bring everything grinding to a halt if the foundry could not meet the requirement. By contrast, threshold voltage for digital circuits is weighted lower since a difference here has less impact. Weighting needs to be defined based on the design objectives of the circuit, e.g. digital, mixed-signal, etc. Note that the average of all weights is 1.0. Each parameter is also assigned a compatibility factor (c). 100 percent is assigned for each parameter meeting the requirement. Values less than 1.0 are assigned (shown highlighted in Tables 1 and 2) for parameters that are not 100 percent compatible. When the weighted average is taken, the index number provides a confidence level of compatibility and can be easily compared for other technologies. Highlighted parameters need close assessment for compatibility. An index value of 1.0 implies full compatibility for the parameters evaluated. In our experience, index values greater than 0.8 generally represent good candidates for a physical port.

Table 2
Foundry selection spreadsheet -- layout design rules
Layout Rules	Weighting (w)	Design Requirement	Foundry Technology	Compatibility Factor (c)	c*w
Raw pitch active	1	2.4	2.2	1	1.00
Raw pitch poly gate	1	2.0	2.0	1	1.00
Raw pitch metal 1	1	2.2	2.2	1	1.00
Raw pitch metal 2	1	2.6	2.2	1	1.00
Raw pitch metal 3	1	3.0	4.0	0	0.00
N+ to p+ across well edge	1	5.0	4.8	1	1.00
Contact size	1	0.8	0.7	1	1.00
Via 1 size	1	0.8	0.8	1	1.00
Via 2 size	1	0.8	0.8	1	1.00
Metal 1 ovlp contact	1	0.5	0.4	1	1.00
Metal 1 ovlp via 1	1	0.5	0.4	1	1.00
Metal 2 ovlp via 1	1	0.5	0.4	1	1.00
Metal 2 ovlp via 2	1	0.5	0.4	1	1.00
Metal 3 ovlp via 2	1	0.5	0.6	0	0.00
Average	1			Index = 0.86

Porting algorithms Phase two is to establish the algorithms needed to convert the original GDSII layers to masks for the alternative source. Due to the process commonality found in most contemporary CMOS processes many layers can be mapped one for one with sizing adjustments to compensate for process biases. For example, the metal-1 layer on process A maps directly into the metal-1 layer of process B with additional sizing needed to match post processed dimensions set by the original design. At the same time, Boolean manipulation of data may be needed to comply with the layout design rules of the backup foundry. An example is to modify the amount of metal overlap around contacts or vias to comply with process B alignment and process tolerances. Certain layers, however, do not always map one to one. For example, if the original GDSII used drawn "n+" and "p+" diffused layers, these may need to be converted to three new layers for process B with Boolean manipulation: namely active area, p+, and n+ implant layers. In doing so, one must avoid creating regions of polysilicon or active regions that are inadvertently counter-doped thereby incurring a yield or reliability risk, etc.

Figure 2. Consideration of transistor and interconnect performance maximizes probability of success in performing a physical port.

Performance matching Validating performance with the foundry technology can be represented as a resource vs. probability of success trade off as shown in Figure 2.

Process Level. The most rudimentary approach is simply to set the transistor gate lengths on the ported design identical to the original, and otherwise comply with the layout rules of the foundry technology. No attempt is made to modify the design to compensate for technology differences that may impact performance. While this "hands-off" approach requires very little intervention, clearly there is a high risk of a severe performance or functionality mismatch.

Device Level. The second approach is to blanket-adjust the polysilicon gate lengths to match the saturation currents of the original technology (i.e.; the n-channel and p-channel gate lengths are set such that the current drive per micron of transistor width is the same across both technologies). While this partially compensates for process differences there is still risk of non-compliance since no attempt has been made to compensate for other technology differences such as interconnect and junction capacitance.

Chip Level. The most complete verification is to simulate critical paths, including macro cells such as RAM access, self timed or asynchronous paths and to do this at typical, fast and slow process corners. While this requires a simulation study it provides for a higher probability of success and opens up additional degrees of freedom in making design modifications to ensure performance. For example, in addition to varying channel length to modulate performance, one may also adjust channel width, interconnect linewidths, to vary area and coupling capacitance, etc. Provided the minimum design rule line widths in the interconnect are not violated, narrowing the metal linewidths is an effective way of reducing capacitance on long metal runners.

Design rule and technology issues As stated earlier, many technology and design rule issues could potentially bring a halt to an otherwise successful port. These may often be overcome, however, by investigating alternatives and other options. Table 3 highlights our actual experiences and work-around methods. The list of potential issues is never ending, and these represent but a few examples.

As described, the physical port option provides for extremely low cost and time efficient method of design transfer. In our experience, once a technology has been targeted and there is agreement from both design house and foundry to do business, it takes about three months to demonstrate tested first silicon. A comparative schedule is shown in Figure 3. The periods required to complete the ports must overlap to achieve this duration.

This schedule also assumes a five-week accelerated cycle time for silicon and mask making (including shipping), which is offered by some foundries at premium pricing. Much of the effort in executing the port is in week one. Running the SPICE simulations to define the correct device and interconnect sizing to meet performance targets takes two weeks. Defining the GDSII layer conversion algorithms and evaluating violations with the foundry and writing the various post processing, design rule checking and verification command files. This work needs to be completed in advance of the port and may take four to six weeks to complete and debug, depending on resources and the degree of difficulty and/or deviation from standard design rules, etc. In this example we were using Dracula (Cadence Design Systems; San Jose, Calif.) and Chipgraph ( Mentor Graphics ; Wilsonville, Ore.) tools. Once the conversion algorithms and procedures are in place, the overall cycletime may be reduced for subsequent designs. Incrementally, product qualification cycles typically require a 1,000 to 2,000 hour operating lifetest. Overall technology qualification cycletimes may be reduced by utilizing product generic qualification data or reduced substantially by using "feature based qualification" methods which are gaining significant favor in the industry for time to market advantage.

Table 3
Technology issues examples
Issue	Substrate type polarity mismatch. (Foundry technology utilizes substrate type of opposite polarity to original.)
Risk	Physical port possible if design is compatible with both polarities.
Opportunities	Provided the original design contains both n-well and p-well data and both are biased fully, it may be possible to switch substrate types by utilizing the correct well data during maskmaking. Most foundry technologies use p-type substrates where the use of digitized n-well data is optimal. P-well digitized data may be considered with the risk of reduced yield due to the large "chip-sized" n-well areas that result. In each case issues to consider include the use of wells as resistors, latchup rules and package to die connectivity assumptions.
Issue	Free vias (Foundry does not permit unrestricted placement of vias adjacent to polysilicon runners.)
Risk	CMOS technologies that lack aggressive dielectric planarization require restrictions on the placement of vias close to polysilicon lines. Polysilicon in the vicinity of field oxide edges creates a severe topological step for the successful patterning of vias. This may result in incomplete vias, distorted vias or partially opened vias. Consequently there is a risk to yield and via reliability.
Opportunities	From a design stand point there may be an opportunity to move vias slightly within the metal "dog-bone." This may be done algorithmically with Boolean manipulation. While this may provide relief for some via situations, it cannot cure all violations. Additional relief is possible by negotiating specific, low-risk cases with the foundry. Whilst the most severe cases need to be avoided, vias that reside on top of polysilicon, between two closely spaced polysilicon lines or at the base of the dielectric slope, are not subject to severe distortion. Increasing metal-1 and metal-2 overlaps around the via will provide added margin.
Issue	Buried contacts. (Original design utilized buried contacts in SRAM core cells, not available at foundry)
Risk	Obviously the circuit will not operate without redesigning the cells that contain them.
Opportunities	Since in most logic or ASIC circuits there is a relatively limited number of RAM elements, it is not unreasonable to re-design the core cell to eliminate the buried contacts. To avoid costly chip redesign, this must be done keeping the redesigned cell size identical to the original. In this way the new cell becomes a straight-forward transplant. It is not likely that a foundry will agree to process buried layers as it represents a major process change.
Layout Design Rule Example
Issue	S/D implant generation
Risk	Partially undoped or counterdoped junctions are subject to leakage and a yield or reliability hazard.
Opportunities	If the n+ and p+ implant layers are not unique drawn layers in the original data, they must be generated. This may be done algorithmically from the active n+, active p+ regions and well data. By ensuring that that digitized data on the n+ and p+ implant regions do not overlap and that the implant overlap of active regions complies with the foundry design rules, the risk of leakage is minimized. Further, by making both implant masks dark field (implant species masked from field regions) there is reduced risk of leakage and double implanting.
Reliability Rules
Issue	I/O ESD protection
Risk	Marginal or unacceptable ESD or EOS (electrical over stress) protection on I/O cells, resulting in destroyed or weakened I/Os.
Opportunities	Effective ESD / EOS protection to 1- to 2kV is a function of the chip environment, the I/O protection design and layout, and the process technology and films. The main risk in porting ESD designs is the change in process technology. If the new technology incurs a significant change in film resistivities or device characteristics, in particular the gain or breakdown voltages of the ESD protecting devices, then there is added risk. This is especially important for diffused or polysilicon paths that are designed to limit current or to dissipate heat due to an ESD event. More subtle differences in silicon or gate oxide quality may substantially impact the level of protection also. Additionally, the foundry may offer an ESD implant option intended to improve the level of protection.
Issue	Antenna rules compliance
Risk	In process gate oxide damage resulting from implant or plasma sources leading to a yield or gate dielectric reliability hazard.
Opportunities	Most silicon foundries are attempting to control their processes sufficiently to minimize the risk to gate oxides resulting from plasma damage. If the phenomenon cannot be 100 percent controlled by process adjustments then the foundry may resort to design rule constraints for complete protection. These usually come in the form of limiting the amount (area) of metal interconnect tied to a polysilicon gate, for each incremental metal layer. Ratios of metal to polysilicon in the range of 25:1 to 100:1 are normal. If the original design was not laid out without antenna rules in mind then the design is subject to charging risks. With the physical port approach, one wants to avoid a costly re-route to comply with the rules. The opportunity is to DRC for interconnect paths which exceed the ratio rule for each metal layer. A "jumper" in the subsequent metal layer may be made manually to meet the rule. Since the violations are most likely to occur in routing channels this manual correction is relatively trouble free. Most foundries will concede that any metal layer which directly connects a gate to a diode (e.g. a transistor drain) is immune from the ratio requirement.
Performance & Timing
Issue	Device Characteristics mismatch
Risk	Transistor and capacitance parameters, if mismatched against the original design assumptions, may create functionality or performance difficulties -- usually at process distribution corners.
Opportunities	All silicon foundries will provide SPICE files and interconnect RC data for their technologies. It is important that critical paths, paths subject to race conditions, self-timed paths (particularly asynchronous operation), paths sensitive to levels such as RAM bit lines and sense amplifiers, latches and I/O buffers, are simulated at typical and fast and slow process corners. Since there are few degrees of freedom in making design changes it may be possible to set the polysilicon transistor gate length optimally. It is further recommended that split conditions for polysilicon and threshold voltage be applied in the first prototype silicon. This will provide a higher degree of confidence that the design will operate at the process corners correctly. Process control charts from the foundry also provide the actual spread on device parameters that the technology exhibits. Technology areas for special caution would include transistor drive strength, threshold voltage or resistance or capacitance values deviating from the original assumption by more than 10 percent, or any electrical shift caused by major technology differences such as the use of silicided silicon and polysilicon or tungsten interconnect as examples.

Physical port as a valid option The physical port approach to establishing alternative foundry sourcing has been demonstrated as a viable and practical technique. It minimizes the need for engineering resources needed to redesign a chip while offering a three-month time to first silicon capability. While technology compatibility issues must be dealt with in performing such a port, we believe that if carried out with performance and manufacturing objectives in mind, it provides for optimal low-cost and time-to-market. The physical port approach eliminates the need for extensive redesign work reducing schedules and costs. To make the port successful, however, expertise in the areas of process technology, design rules, device reliability and mask making are necessary in order to make the correct design and technology risk trade-offs.

Figure 3. Foundry selection, design conversion and first silicon can be realized within three months.

Acknowledgments The authors would like to thank the many contributors within Technology Development, IC Design, IC Applications, IC CAD and Product Engineering functions at Unisys, and the Systems Technology Group at Rancho Bernardo, Calif., without whose efforts it would not have been possible to demonstrate and make the physical port approach productive. *

Brian Henderson is a program manager responsible for foundry ASIC sourcing, Rakesh Kumar directs technology development, Riko Radojcic has responsibility for all aspects of IC reliability, and Minh Bui is a design technologist responsible for design aspects of physical ports; all at Unisys Corp. They are presently with Cadence Design Systems Design Center in San Diego, California. Contact the authors at (619) 451-4932 by phone and at henderson@rb.unisys.com by e-mail with questions or comments on porting designs between foundries.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  April 1995