ASIC Technology

FPGAs Can Meet ASIC Design Requirements

In the future, FPGAs will have to become more "gate array-like" to allow the use of EDA tools.

by Tim Saxe

EDA tools developed around gate arrays, so it is natural that they have become tuned to gate array characteristics. To facilitate the use of EDA tools with FPGAs, the FPGAs will have to become more "gate array-like."

The first required change is granularity. A typical CMOS ASIC has a basic cell of four transistors. Each cell is assigned a gate equivalency of one, since a two-input NAND can be implemented with one basic cell. Synthesis is, of course, based on logic optimization techniques, such as BDDs, that favor relatively simple logic functions such as "and," "or," and "and-or-invert." As a result, most synthesized netlists contain a large number of relatively simple logic functions. The average macrocell in a synthesized netlist requires a little more than two basic cells to implement. Storage elements, such as flip-flops, are typically the largest elements in the netlist. Typically 20 to 40 percent of the basic cells used in an ASIC design are used to implement the storage elements. The remaining 60 to 80 percent are used for the logic elements.

In contrast, a typical SRAM FPGA is built around a basic unit consisting of a four-input look-up table (LUT) and a flip-flop. These basic units are clustered in groups of two, four, or eight, depending on the vendor. The clusters are then connected by some routing structure. Since the four-input LUT can implement any function of four variables, it is generally considered to be equivalent to about five gates of logic, and the flip-flop to be about seven gates. The total is therefore 12 gates per basic unit. Obviously this capacity of 12 gates per basic unit is only obtained when 56 percent of the equivalent gates are used for flip-flops. Since most netlists have only 20 to 40 percent of their equivalent gates used for flip-flops, about half of the flip-flops will typically go unused. Thus, in practice only about 8.5 gates can be packed into a basic unit.

In addition, synthesis does not use the four-input LUT as effectively as a human can. In fact, whereas humans seem to fit about five gates per LUT, synthesis only fits three to four gates per LUT. This further slashes the effective gates per basic unit. It is not uncommon to see synthesized designs that fit only four to six of the available 12 gates per basic unit.

The mismatch between synthesis and the large-grained structures of the SRAM FPGAs can be tackled in several ways. One way is to revamp synthesis to better match the large cell. Another is to add large parameterized cells to synthesis. Still another is to leave synthesis alone and add technology mapping. A final way is to change the granularity of the FPGA. Revamping synthesis is unattractive as it moves the solution away from the mainstream. Adding parameterized cells does not solve the general problem, and makes technology independence harder to achieve.

Technology mapping (taking several smaller cells from an ASIC netlist and combining them into a single basic unit) is a popular solution to the synthesis problem. In addition to fitting well into existing flows, it has the advantage of technology independence. Technology mapping is essentially the same as "bin packing," however, which is a known hard problem. Technology mapping also has the potential for nasty side effects. For example, a good packing may not be very routable, as logic elements that should be far apart may be placed into the same LUT.

Timing will also vary significantly, depending upon the actual packing. What's more, small design changes can result in radically different packings, and hence radically different timing. The final problem with technology mapping is that it makes name mapping very difficult. Names that exist in the original netlist may not exist in the mapped netlist, and the mapped netlist my create new names and nets.

Changing the granularity of the FPGAs, while an obvious solution, is not easy. Granularity is driven by the available technology. ASICs have a low granularity because their routing overhead is small in area and performance. SRAM FPGAs have a large routing overhead. Connectivity is created by switches that are both large in area and performance overhead. Large routing overhead forces the FPGA vendor to amortize the routing overhead over a large cell. In fact, the great similarity of the basic units used by the SRAM FPGA vendors suggests that the combination of a four-input LUT and a flip-flop is optimum for the overhead associated with an SRAM switch. Antifuse FPGAs also have a large overhead, although in this case it turns out to be the programming logic overhead. The actual antifuse itself is very small, typically the size of a via; however, since programming the antifuse requires high voltage and current, the programming circuitry requires large transistors that consume area and capacitively load the routing structures. The result is both a performance overhead and an area overhead. Consequently antifuse devices have about the same effective gates per area as SRAM devices. Achieving a fine-grained FPGA requires a new interconnection technology.

An FPGA solution for ASIC designers To be successful in the ASIC market, an FPGA solution needs to stay in the mainstream. Therefore, it must effectively utilize existing ASIC design systems and methodologies. This implies a fine-grained architecture similar to that of a CMOS ASIC, which in turn implies a new technology. The new technology will have a smaller, higher performance switch will allow the new FPGA to achieve high density with a fine grain size, which will result at last in a synthesis-friendly, high-capacity FPGA.

An FPGA solution for ASIC designers To be successful in the ASIC market, an FPGA solution needs to stay in the mainstream. Therefore, it must effectively utilize existing ASIC design systems and methodologies. This implies a fine-grained architecture similar to that of a CMOS ASIC, which in turn implies a new technology. The new technology will have a smaller, higher performance switch than existing FPGAs. A small switch will allow the new FPGA to achieve high density with a fine grain size, which will result at last in a synthesis-friendly, high-capacity FPGA.

Tim Saxe is VP of engineering at Gatefield, a Zycad corporation.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  July 1995