EDA Consumer Advocate Diary

An Independent Critique of Two New Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Tools John Cooley, founder of the outlaw E-mail Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Users' Group (ESNUG), summarized his review with "Although I yawned at DesignSource, I thought HDL Advisor was sexy." by John Cooley

Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys (Mountain View, CA) is trying to push designers out of the gate-tweaking stage and into higher-level approaches. That is, they're interested in moving designers into doing things like considering the effects of test, power, and physical design characteristics at the source level prior to synthesis. The two major products that are the foundation of this new approach are DesignSource and HDL Advisor.

Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys 's DesignSource Essentially, DesignSource is a block diagram schematic editor with the design database management idea thrown in having the ability to associate HDL source code with synthesis scripts, Verilog/VHDL simulation test beds, and their resulting outputs in one database.

It has many bells and whistles, including a hierarchy browser, a rather simple Verilog/VHDL template generator, a block-level connectivity checker, a VHDL-specific "attribute" spreadsheet editor, and an ability to fire up simulation and synthesis scripts as a front-end to VSS and Design Compiler. The Block Editor automatically propagates VHDL information like names, types, and attributes to the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys VSS simulator.

In reviewing DesignSource, I felt I wasn't looking at anything new but something more like a potpourri of ideas and parts of other tools that had been kicking around for some time in the EDA community. It just sang out Cadence Composer, Mentor Design Architect, Viewlogic ViewDraw, Summit Design , Escalade, parts of Intergraph's tool offerings, and even the old Racal-Redac's Visula schematic editor.

The Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Verilog/VHDL template generator seemed rather primitive at best. Based on what was entered in the graphical Block Editor, for VHDL it threw down a simple piece of empty boilerplate ENTITY/ARCHITECTURE; for Verilog it spits out an empty module and its associated input/output statements. The user is then left on his own with the "vi" editor to fill in these empty pieces of boilerplate with his sophisticated codings of state machines, data paths, controllers, etc.

My question is: If a user can't create this initial no-brainer type of boilerplate in 10 minutes on his own, how can he be trusted with coding the rest of the design?

For designers interested in something a little more involved in writing VHDL, I'd suggest you take a look at Insight from Summit Design (Beaverton, OR). Insight is best described as interaction with a living, breathing VHDL Language Reference Manual­a hog-wild VHDL syntax thingy.

For Verilog, Cadence Design Systems (San Jose, CA) reports having a similar language-sensitive editor in its Verilog-XL Design Environment, with an additional waveform viewer and Verilog debugger thrown in. Super-cheap users can even look into the free GNU-EMACS editor with Verilog/VHDL-specific settings.

The carefully-manage-all-your-ASIC-design's-associated-files concept is as old as Unix software is. For many a year, ASIC designers have been using free Unix utilities like SCCS and RCS to keep track of various revisions of their source Verilog/VHDL files, their synthesis scripts and the changes in their Verilog/VHDL testbenches for their designs. (SCCS and RCS design database management is characterized by designers checking in and checking out various associated design files. Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys 's DesignSource doesn't have check in/check out; it just associates various design files together.)

In my opinion, DesignSource isn't worth $7,000, much less the $17,000 they're asking for it.

Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys 's HDL Advisor Inasmuch as I reserve the right to publicly yawn at DesignSource because it seemed to be an overpriced Cadence Composer copycat product for Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys , I also reserve the right to publicly applaud Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys for creating a unique, new, interesting, and useful tool with its HDL Advisor.
It's hot!

One of the early questions that I had when first taking an in-depth look at HDL Advisor was: Is this just warmed over, productized source-to-gates?

Source-to-gates was a feature that offered Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys customers a very crude correlation between a group of gates from synthesis and where in the source Verilog/VHDL it sort of thought it came from. Source-to-gates didn't work very well because synthesis would add and remove gates all the time to fit some timing or area constraint.

Well, HDL Advisor turned out to be much more of a true analysis tool focused on the before-synthesis problem of coding one's Verilog/VHDL design. Here's what I saw in HDL Advisor:

HDL Browser This "home" window lets you examine your source Verilog/VHDL and how various specific lines of source code relate to graphics/reports you generate in other windows. The Hot Cursor and Selection Inspector (described later) play a significant role here, too.

At the pre-synthesis point you can keep track of timing via the number of logic levels your source Verilog/VHDL would create, a rough area estimate under the component count heading and your source Verilog/VHDL-related connectivity issues like fan-in and fan-out. Note: this is before synthesis.

At the post-synthesis point you get to keep track of area, power, timing violations in relation to the constraints you gave the design, and connectivity issues like fan-in, fan-out and capacitance.

Histogram and Profiler Histogram and Profiler are two graphics packages that display the pre- and post-synthesis data described above in an intelligent and useful manner for the ASIC designer. Let's say I'm interested in timing issues for my pre-synthesis Verilog source code. (Since there's no real timing information at the pre-synthesis phase, the next best thing that correlates to timing is the number of logic levels my piece of Verilog would have if mapped to gates.)

I'd fire up the histogram to show the distribution of pre-synthesis logic levels in my design. Click on a specific histogram bin, and voilà!, the list of specific design data points in that bin are listed with the HDL browser showing the associated source Verilog code highlighted.

Profiler works in a similar manner, but as a single vertical bar broken into segments showing percentages. It's useful, for example, for tracking how much area various parts of your source Verilog/VHDL results in.

Path Browser and Logic Inspector Once I've identified an interesting issue with my Verilog source (like lots of high fan-out points discovered from looking at the Histogram for fan-out), I can chase these problems throughout my Verilog source by using the Path Browser, which explores pure connectivity.

If I was curious down to the gate level, I'd fire up Logic Inspector to see a Boolean gate-level representation of what I'm interested in. (All the time, every point I touch in these explorations is cross-referenced and highlighted in the source in HDL Browser.) Also, if I'm interested in chasing something like post-synthesis capacitance, I can use Path Browser and Logic Inspector in a similar manner.

Hot Cursor and Selection Inspector Hot Cursor and Selection Inspector run throughout all of the windows in HDL Advisor. Essentially, a hot cursor tells the user quickie information without having to "click" on anything. Just run the cursor over something and it'll tell you a useful snippet like a module name on a particular part displayed in Profiler or the Boolean expression at a specific point seen in Logic Inspector.

Selection Inspector is a follow-up window that spews out as much information as is known about a point if it's "clicked" by the cursor: stuff like name, fan-in, fan-out, logic levels, area, hierarchy path, timing slack, power­whatever it knows at the time.

With its focus on getting feedback to the designer while he's writing his Verilog/VHDL source code, HDL Advisor helps circumvent the dreaded Synthesis Iteration Hell. That is, there are many ASIC design teams that first write their Verilog/VHDL code, spend months verifying its functionality with reams of regressions, and then take this golden source code to synthesis.

If the golden code runs into problems, designers will literally spend weeks or even months chasing down all sorts of settings and switches for Design Compiler to avoid having to change their errant source Verilog/VHDL. HDL Advisor promotes better coding styles for synthesis while the source code is being written.

A few of the old-time Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys customers may say, "Sounds like a good tool for beginners. I don't need it because I already know what does and doesn't get you in trouble for Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys . " They're missing a crucial point, though. It's one thing to know that "nets with high fan-outs are bad news"; it's another to know exactly which nets fit in that category in your specific design before synthesizing. That is, HDL Advisor lets you ask meaningful questions on large and complex hunks of Verilog/VHDL source code like, Where are the longest paths? What modules do they go through? What are the fan-ins and fan-outs at this point? Where do they lead? How does the timing slack or capacitance relate back to the source? What's the Boolean equation in the design?

Instead of burning up brain cells trying to figure out how your code (or worst yet, some source code you "inherited") will be digested by the Synthesis Monster, this tool quickly lets you know where your code's hot spots are and where they aren't.

I recommend checking out Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys 's HDL Advisor because it lets you check your design even before you simulate (much less synthesize) it.

Summary DesignSource is a Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys version of Cadence's Composer: Personally, I'd wouldn't buy either product (with their hefty asking prices of $17,000 and $14,000) for what little these block schematic editing tools with revision control do. You can get free revision control using Unix's SCCS/RCS, and the wimpy coding templates created by the block schematic editors can be made by hand in 10 minutes with "vi." Mind you, if you're not disciplined enough to handle file management and revision control on your own, immediately buy DesignSource, because you'll lose significant time and energy and money and sleep
without it.

On the other hand, Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys HDL Advisor is definitely an interesting new type of tool altogether. I'd recommend giving it a look-see if you're a newbie designer or an old pro. HDL Advisor lets you quickly know where the hot spots are and where hot spots aren't in your Verilog/VHDL source code­even before you simulate (much less synthesize) the design. Check it out.

From his sheep farm, John Cooley founded and runs the outlaw E-mail Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys User's Group (ESNUG) an independent, free, grassroots, electronic weekly newsletter with over 3,300 subscribing IC designers. (So independent, in fact, that Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys 's lawyers tried to shut it down when it started some four years ago.) He is an ASIC and FPGA design consultant and can be contacted at "jcooley@world.std.com" or (508) 429-4357.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  June 1995