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EDA Consumer Advocate Diary
I knew I had hit a nerve. Usually when I publish a candid review of a particular conference or EDA product I get around 85 messages in my e-mail. Buried in my review of the recent Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys User's Group meeting, I briefly reported that eight of the nine Verilog designers managed to complete the conference's design contest yet none of the five VHDL designers could. I apologized for the terseness and promised to do a detailed report on the design contest at a later date. Since that review, my e-mail "in" box has been a veritable VHDL/Verilog Beirut with 169 replies. Once word leaked that the detailed contest write-up was going to be published in the DAC issue of Integrated System Design , I started getting phone calls from the chairman of VHDL International, Mahendra Jain, from the president of Open Verilog International, Bill Fuchs, and others. I went ballistic when VHDL columnist Larry Saunders approached this magazine's editor-in-chief for an advanced copy of my design contest report. He felt I was "going to do a hatchet job on VHDL" and wanted to write a rebuttal that would follow my article... all this before I had even written one damned word.
Because I'm an independent consultant who makes his living training and working
both
HDLs, I'd rather not go through a VHDL Salem witch trial where I'm publicly accused of being secretly in league with the Devil to promote Verilog. Instead, I'm going to present
everything
that happened at the design contest, warts and all, and let you judge. At the end of the evidence, I'll ask you, the jury, to e-mail me your verdict, which I can publish in my column in a future issue of this magazine.
Table 1. Note: none of the five VHDL designs succeeded. The unexpected results Contestants were given 90 minutes to use VHDL or Verilog to create a gate netlist for the fastest fully synchronous loadable 9-bit increment-by-three decrement-by-five up/down counter that generated even parity, carry, and borrow. Of the nine Verilog designers in the contest, only one didn't get to a final gate-level netlist, and that was because he tried to code a look-ahead parity generator. Of the eight remaining, three had netlists that missed on functional test vectors. The surprise was that, during the same time, none of five VHDL designers in the contest managed to produce any gate-level designs. Not VHDL newbies vs. Verilog pros The first reaction I get from the VHDL bigots (who weren't at the competition) is: "Well, this is obviously a case where Verilog veterans whipped some VHDL newbies. Big deal." Well, they're partially right. Many of those Verilog designers are damned good at what they do; but so are the VHDL designers. I've known Prasad Paranjpe of LSI Logic (Milpitas, Calif.) for years. He teaches VHDL with synthesis classes at U.C. Santa Cruz University Extension. He was VP of the Silicon Valley VHDL Local Users' Group, has been a full-time ASIC designer since 1987, and has designed real ASICs since 1990 using VHDL and Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys . (His private e-mail address is "VHDL@ix.netcom.com" and home phone is 555-VHDL.) ASIC designer Jan Decaluwe has a history of contributing insightful VHDL and synthesis posts to ESNUG while at Alcatel (Hickory, N.C.) and later as a founder of the ASIC design house Easics (Brussels, Belgium) whose motto is "The VHDL design company."
Another LSI Logic/VHDL contestant, Vikram Shrivastava, has used the VHDL/
Synopsys
.com/isdweb/&lf=isd-sendtolog">
Synopsys
design approach since 1992. These guys aren't newbies.
 Figure 1. This block diagram outlines the functionality of the design used in the competition.Creating the contest I followed a double blind approach to putting together this design contest. That is, I had VHDL columnist Larry Saunders and Verilog columnist Yatin Trivedi, both of Seva Technologies (Fremont, Calif,), comment on the design contest. Unknown to them, however, I also had Ken Nelsen (a VHDL-oriented methodology manager from Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys ) and Jeff Flieder (a Verilog-based designer from Ford Microelectronics [Colorado Springs, Colo.]) also help check the design contest for any conceptual or implementation flaws. My initial concern was to not have a situation where the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Design Compiler could quickly complete the design by just placing down a DesignWare part, yet I didn't want contestants trying (and failing) to design some fruity, off-the-wall thingy that no one truly understood. Hence, I was restricted to "standard" designs that all engineers knew, but with odd parameters thrown in to keep DesignWare out of the picture. Instead of a simple up/down counter, I asked for an up-by-three and down-by-five counter. Instead of eight bits, everything was nine bits. The even PARITY, CARRY, and BORROW requirements were thrown in to give the contestants some space to make significant architectural trade-offs that could mean the difference between winning and losing. The counter loaded when the UP and DOWN were both "low," and held its state when UP and DOWN were "high"--exactly the opposite of what 99 percent of the world's loadable counters traditionally do. To spice things up a bit more, I chose to use the LSI Logic 300K ASIC library because wire loading and wire delay are significant factors in this technology. Having the "home library" advantage, one savvy VHDL designer, Prasad Paranjpe, cleverly asked if the default wire loading model was required (he wanted to use a zero wire load model to save in timing). I replied: "Nice try. Yes, the default wire model is required." To focus on design and not verification, contestants were given equivalent Verilog and VHDL testbenches provided by Seva Technologies. These testbenches threw the same 18 vectors at the Verilog/VHDL source code the contestants were creating, and if it passed, their design was judged "functionally correct" for contest purposes. VHDL contestants had their choice of VSS 3.2b from Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys (Mountain View, Calif.) or Leapfrog VHDL 2.1.4 from Cadence (San Jose, Calif.), or both; Verilog contestants had Cadence Verilog-XL 2.1.2 or VCS 2.3.2 from Chronologic Simulation (Los Altos, Calif.), plus their respective Verilog/VHDL design environments. (Bob Hunter, the CEO of Model Technology [Beaverton, Ore.], was too paranoid about the possibility of Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys employees seeing his VHDL to allow it in the contest.) LCB 300K rev 3.1A.1.1.101 was the LSI Logic library. I was concerned that some designers might not know that an XOR reduction tree is how one generates parity, but Larry, Yatin, Ken, and Jeff all agreed that any engineer not knowing this shouldn't be helped to win a design contest. As a last minute hint, I put in every contestant's directory an "xor.readme" file that named the two XOR gates available in the LSI 300K library (EO and EO3) plus their drive strengths and port lists. The contest took place in three sessions over the same day. To keep things equal, my guiding philosophy throughout these sessions was to conscientiously not fix or improve anything between sessions... no matter how frustrating.
Larry and Yatin thought that the contest would be too easy, while Ken
and Jeff thought it had just about the right amount of complexity. I asked them if they saw any Verilog or VHDL specific "gotchas" in the contest. All four categorically said "no."
Listing 1. All I/O events happen on the rising edge of CLOCK. Murphy's law Once the contest began, Murphy's Law ("If anything can go wrong it will") prevailed. Because we couldn't get the Sun and HP workstations until a terrifying three days before the contest, I lived through a nightmare domino effect on getting all the Verilog, VHDL, Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys and LSI libraries in and installed. I had to drop the Hewlett-Packard (Palo Alto, Calif.) machines because most of the EDA vendors couldn't cut software keys for HP machines as fast as they could for Sun Microsystems (Mountain View, Calif.) workstations. The LSI 300K Libraries didn't arrive until an hour before the contest began. The Seva guys found and fixed a bug in the Verilog testbench (which didn't exist in the VHDL testbench) some 15 minutes before the contest began. Some 50 minutes into the first design session, one engineer's machinewhich also happened to be the license server for all the Verilog simulation softwarecrashed. (Luckily, by this time all the Verilog designers were deep into the synthesis stage.) Unfortunately, the poor designer who had his machine crash couldn't be allowed to redo the contest in a following session because of his prior knowledge of the design problem. This machine was rebooted and used solely as a license server for the rest of the contest. The logistics nightmare once again reared its ugly head when two designers innocently asked: "John, where are your Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys manuals?" Inside I screamed to myself: "OhMyGod! OhMyGod! OhMyGod!"; outside I calmly replied: "There are no manuals. You have to use the on-line docs available." More gremlins danced in my head when I realized that six of the eight data books that the LSI library person brought weren't for the exact LCB 300K library we were usingthese data books would be critical for anyone trying to hand-build an XOR reduction treeand one Verilog contestant had just spent 10 precious minutes reading a misleading data book. (There were two LCB 300K, one LCA 300K, and five LEA 300K databooks.) Verilog designer Howard Landman noted: "I probably wasted 15 minutes trying to work through this before giving up and just coding functional parity, although I used parentheses in hopes of Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys using 3-input XOR gates." Just as things couldn't get worse, everyone got to discover that when Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys 's Design Compiler runs for the first time in a new account, it takes a good 10 to 15 minutes to build your very own DesignWare cache. Verilog contestant Ed Paluch, a consultant, noted: "I thought that first synthesis run building [expletive deleted] DesignWare caches would never end! It felt like days!" Although, in my opinion, none of these headaches compromised the integrity of the contest, at the time I had to continually remind myself: "To keep things equal, I can not fix nor improve anything no matter how frustrating."
Judging the results
Because I didn't want to be in the
business of judging source code
intent
, all judging was based solely on whether the gate level passed the previously described 18 test vectors. Once done, the design was read into the
Synopsys
.com/isdweb/&lf=isd-sendtolog">
Synopsys
Design Compiler and allconstraints were removed.Then I applied the command "
Kurt Baty, a Verilog contestant and well-respected design consultant, registered a vocal double surprise because he knew his design was of comparable speed but had failed to pass the 18 test vectors. An on-the-spot investigation showed that Kurt had accidentally saved the wrong design in the final minute of the contest. Further investigation then yielded that the 18 test vectors didn't cover exactly all the counter's specified conditions. Larry's "winning" gate-level Verilog based design had failed to meet the spec of holding its state when UP and DOWN were high, even though his design had successfully passed the 18 test vectors. If subjective visual inspection of the source code were part of the judging criteria, Verilog designer Steve Golson would have won. Once again, I had to reiterate that all designs that passed the testbench vectors were considered "functionally correct" by definition. What the contestants thought Despite NASA VHDL designer Jeff Solomon's "I didn't like the idea of taking the traditional concept of counters and warping it to make a contest design problem," the remaining 12 contestants really liked the architectural flexibility it had. Verilog designer Mark Papamarcos summed up the majority opinion with: "I think that the problem was pretty well devised. When I first saw it, I thought it would be very easy to implement and I would have lots of time to tune. I also noticed the 2- and 3-input XOR's in the top-level directory, figured that it might be somehow relevant, but quickly dismissed any clever ideas when I ran into problems getting the vectors to match." Eleven of the contestants were tempted by the apparent correlation between known parity and the adding/subtracting of odd numbers. Only one Verilog designer, Oren Rubinstein of Hewlett-Packard Canada (Waterloo, Ont.), committed to this strategy but ran way out of time. Once home, Kurt Baty helped Oren conceptually finish his design while Prasad Paranjpe helped with the final synthesis. It took about seven hours brain time and eight hours coding/simulation/synthesis time (15 hours total) to get a final design of 3.05ns and 1,988 gates. Observing that it took ten times the original estimation of 1.5 hours to get a 22 percent improvement in speed, Oren commented: "Like real life, it's impossible to create accurate engineering design schedules."
Two of the VHDL designers, Prasad Paranjpe and Jan Decaluwe, complained of having to deal with type conversions in VHDL. "I can't believe I got caught on a simple typing error," Prasad confessed. "I used IEEE
Verilog competitor Steve
Golson outlined the first-get-a-working- design- and-then-tweak-it-in-synthesis strategy that most of the Verilog contestants pursued. "As I recall, I had some stupid typos that held me up," he says. "I also had difficulty with parity and carry/borrow. Once I had a correctly functioning baseline design, I began modifying it for optimal synthesis. My basic idea was to split the design into four separate modules: the adder, the 4:1 MUXes, the XOR logic (parity and carry/borrow), and the top counter module which
contains only the flops and instances of the other three modules. My strategy was to first compile the three (purely combinational)submodules individually. I used a simple '
Typos and panic hurt the performance of a lot of contestants. Verilog designer Daryoosh Khalilollahi of National Semiconductor (Santa Clara, Calif.) said: "I thought I would not be able to finish it on time, but I just made it. I lost some time because I would get a Verilog syntax error because I had one extra file in my Verilog 'Include' file (
On average, each Verilog designer managed to get two to five synthesis runs completed before running out of time. Only two VHDL designers, Jeff Solomon and Jan Decaluwe, managed to start (but not complete) one synthesis run. In both cases I disqualified them from the contest for not making the deadline but let their synthesis runs attempt to finish. Jan arrived a little late so we gave Jan's run some added time before disqualifying him. His unfinished run had to be killed after 21 minutes because another group of contestants was arriving. (Incidentally, I had accidentally given the third session an extra six design minutes because of a goof on my part. No Verilog designers were in this session but VHDL designers Jeff Solomon, Prasad Paranjpe, Vikram Shrivastava and Texas Instruments' Ravi Srinivasan all benefited from this mistake.) Since Jeff was in the last session, I gave him all the time needed for his run to complete. After an additional 17 minutes (total) he produced a gate-level design that timed out to 15.52ns. After a total of 28 more minutes he got the timing down to 4.46ns but his design didn't pass functional vectors. He had an error somewhere in his VHDL source code.
Failed Verilog designer Kurt Baty closed with: "John, I look forward to next year's design contest in whatever form or flavor it takes, and a chance to redeem my honor."
 Listing 2. The winning Verilog source code. (Note that it failed to meet the spec of holding its state when UP and DOWN were both high.)Closing arguments VHDL bigots may claim "What 14 engineers do isn't statistically significant. Even the guy who ran this design contest admitted all sorts of last minute goofs with it. You had a workstation crash, no manuals, and misleading LSI databooks. The test vectors were incomplete. One key VHDL designer ran into a Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys VHDL simulator bug after arriving late to his session. The Verilog design that won this contest didn't even meet the spec completely. In addition, this contest wasn't put together to be a referendum on whether Verilog or VHDL is the better language to design in; hence it may miss some major issues." The Verilog bigots might close with: "No engineers work under the contrived conditions one may want for an ideal comparison of Verilog and VHDL. Fourteen engineers may or may not be statistically significant, but where there's smoke, there's fire. I saw all the classical problems engineers encounter in day to day designing here. We've all dealt with workstation crashes, bad revision control, bugs in tools, poor planning, and incomplete testing. It's because of these realities I think this design contest was perfect to determine how each HDL measures up in real life. And Verilog won hands down." You the jury... I ask you to please take 10 minutes to think about what you have just read and--in 150 words or less--send your verdict to me at "jcooley@world.std.com." Please don't send me "VHDL sucks!" or "Verilog must die!", but personal experiences or observations that add to the discussion. It's okay to have strong opinions; just back them with something more than hot air. Since I don't want to be in the business of chasing down permissions, my default is: whatever you send me is completely publishable. If you wish to send me letters with a mix of publishable and non-publishable material clearly indicate which is which. John Cooley runs the autonomous E-mail Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Users' Group (ESNUG) from his sheep farm. A regular Integrated System Design columnist, Cooley is an independent ASIC/EDA/FPGA consultant and can be reached at "jcooley@world.std.com" or by phone at (508) 429-4357. integrated system design July 1995[ Articles from Integrated System Design Magazine ] [ ICs and uPs ] [ Custom ICs and Programmable Logic ] [ Vendor Guide ] [ Design and Development Tools ] [ Home ] For advertising information e-mail amstjohn@mfi.com Comments on our editorial are welcome. Copyright © 1996 - Integrated System Design Magazine |
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