EDA Consumer Advocate Diary

Rorschach Testing 273 Engineers with the Verilog/VHDL Contest This turned into an amazingly candid study of what engineers are thinking about Verilog and VHDL. by John Cooley

Earlier this year, at the annual Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Users Group meeting, a 90-minute ASIC design contest was held. Using either Verilog or VHDL, the 14 contestants were asked to create a gate netlist for the fastest fully synchronous loadable 9-bit increment-by-3 decrement-by-5 up/down counter that generated even parity, carry and borrow.

Of the nine Verilog designers in the contest, only one didn't get to a final gate level netlist because he tried to code a look-ahead parity generator. Of the eitht remaining, three had netlists that missed on functional test vectors leaving five Verilog designers who got fully functional gate-level designs. The surprise was that, during the same time, none of five VHDL designers in the contest managed to produce any gate level designs.

In the July issue of Integrated System Design , I published a very detailed write-up of the contest. As a sort of industry wide Rorschach test, I asked the readers to e-mail me their background, their vote for whether Verilog or VHDL "won", and the open-ended question of why they thought the way they did.

Figure 1. This contest was like giving engineers a Rorschach ink blot test.

Here's what 273 ASIC design engineers were thinking... DEMOGRAPHICS: A total of 317 letters were received, but only 273 were tabulated; 88 VHDL-only, 76 Verilog-only, 66 bilinguals, and 43 unknown language users. None of the following people's opinions were tabulated: 19 asking only for the contest's test suites, 17 people employed by EDA vendors, three university CS types, a chemistry professor, an EE Ph.D. candidate seeking permission to translate the design contest into Estonian, three EDA sales pitches and one "Christ is Coming Soon!" letter. Four ESDA vendors wrote for the contest specs making great claims in the process but were never heard from again after getting them.

Payback time Because of all the time and energy some the EDA sales staffs put into pushing VHDL onto engineers happy with Verilog, this contest seemed to be a clarion call for Verilog customers (14 to be exact) to tell me the shenanigans they suffered at the hands of these EDA vendors. Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Inc. topped the perpetrator list because they had a Verilog/VHDL synthesis tool but only a VHDL simulator (VSS) to go with it. Hence, their sales staff was quite motivated to creatively work overtime promoting VHDL over Verilog.

Scott C. Petler; Next Level Communications Inc. ­ When I worked at HP Roseville, I remember taking my first Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys training class. The instructor from Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys kept telling us that we were making a grave mistake using Verilog and that EVERYONE who was anyone was using VHDL. (I actually was worried at the time we had chosen the wrong language, and that he was really unbiased. As I look back it is obvious that he was probably a VSS VHDL salesman and did Design Compiler training on the side.) I'm glad we chose Verilog, especially when teaching new engineers and when getting our SW/FW folks (who eat/sleep/breathe "C") to understand the HDL I have written. I would really encourage any new HDL designer to choose Verilog rather than VHDL, since it is much easier to learn, use and eventually master.

I laughed out loud when I saw this next letter. At the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Users Group meeting three years ago, the HP Boise Laserjet VHDL "success" story was a main event. A Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys even used it in a major ad campaign promoting VHDL with synthesis in all the trade journals!

Robert Rust; Hewlett Packard Boise Printer Division ­ I have spent most of my design life (last four years) working on VHDL designs. Recently, I have been forced into the Verilog camp by a vendor. My initial concerns that Verilog would not have the functionality that I needed have been proven wrong. Verilog does what I need better - and the simulators are faster than VHDL simulators.

Since VHDL was driven mostly by the government which has no interest in the productivity of the designers, it is not surprising to see your results from the contest. VHDL syntax hinders progress and does not improve the robustness or quality of the design. The behavioral compilers, not VHDL, make the most sense for doing even more sophisticated design work. Please don't make me be go back to VHDL!

How to not lie with statistics To my surprise, hardly anyone (2 VHDL-only users) tried to say this was statistically insignificant, but four (5 percent) VHDL-only, five (7 percent) Verilog-only, three (5 percent) bilinguals, three (18 percent) EDA vendors, and one (25 percent) professor thought is was mathematically kosher.

Anonymous ­ One question that you have the VHDL bigots make in this "trial" can be completely refuted: the results are statistically significant as the term is usually defined. To say a result is statistically significant, you show that it was very unlikely to be achieved by chance. Given: nine Verilog designers and five VHDL designers, choose eight winners at random. What is the chance that they will all be Verilog designers? Answer: (9/14)*(8/13)*(7/12)*
(6/11)*(5/10)*(4/9)*(3/8)*(2/7)
= 0.002997
= 1/333.7

So there is one chance in 333.7 that this result is purely by chance. We can't argue that this result isn't statistically significant given this figure. This is a greater than 99 percent confidence level. If we take one VHDL designer out (the one who suffered from the VHDL simulator bug), we get (9*8*...2)/(13*12*...6) or 1/143.

From the foundry Rather than risk losing any business or possibly angering customers, six ASIC foundry and three FPGA vendors wrote carefully balanced replies that said effectively: "Whatever the customer wants is right." One former foundry person wrote on condition of anonymity:

Anonymous ­ In a previous life, I worked as an onsite applications engineer for an ASIC vendor. The customer that I supported was developing 17 ASIC's for a large program. The customer chose to develop some of the designs in VHDL and others in Verilog. All were synthesized using Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys . The smallest design was 15 kgates, the largest was 100 kgates. I interviewed the design teams to gather some interesting statistics. Conclusions were:

1. Designs done in Verilog were, without fail, completed faster than those done in VHDL (in terms of gates/manweek).

2. Adding designers to VHDL and Verilog based designs SLOWED the gates/manweek metric, but adding designers to VHDL-based designs had a greater negative impact. (Probably due to data-typing issues.)

3. Single or dual-person design teams outperformed all others.

The designers (80) were of various experience levels, working in groups of two to 10. From end of specification to final signoff, the highest performing was a Verilog team at 15 kgates/manweek, the lowest was a VHDL team with eight gates/manweek!

VHDL'S strategic retreat In the engineering press and on the Internet prior to the Verilog/VHDL Design Contest, the VHDL bigots managed to create an image that the only problem their language of choice had was in convincing the ASIC foundries to provide VHDL libraries. Hence, the big media presence of "VHDL Initiative Towards ASIC Libraries" (VITAL). With the Design Contest results 39 (44 percent) VHDL-only, four (5 percent) Verilog-only, 19 (29 percent) bilinguals, and 14 (33 percent) unknown language users conceded that Verilog "wins" in low level gate-type design, but VHDL "wins" in higher-level abstract design. That is, VHDL is retreating from gate-level design to "own" high-level design. (Just weeks before the Design Contest, VHDL proponents were openly claiming VHDL was just as good at gate-level ASIC design as Verilog was.)

Sean Atsatt; Seagate ­ I've successfully used both languages and think that the results of the contest are directly correlated to the structure of the languages. It exactly mirrors my experiences. Given this, I still prefer VHDL. My first design was with Verilog and on the first day (after I'd taken the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Verilog class) I was able to write usable code that was simulatable and synthesizable. I found the language relatively simple and easy to use, and thus easy to produce results with. When I changed jobs I started using VHDL and have produced several large chips with it. It took me more than a week to get my first VHDL code to compile, not to mention simulate. At first I couldn't stand VHDL, but as time went by I found that it's more structured, verbose and abstract from actual hardware. Although harder to learn and easier to mess up, it's valuable on large projects.

Testing more important For some engineers testing was more important than other issues: 14 (16 percent) VHDL-only and nine (12 percent) Verilog-only stated that their chosen HDL was best for this; nine (14 percent) bilinguals and four (9 percent) unknowns liked VHDL on testing; eight (12 percent) bilinguals and 1 unknown preferred Verilog.

Rick Price; General Instrument Corp. ­ It's clear from the contest that Verilog can get you to a netlist faster than VHDL - period end of story. BUT my experience has shown that the amount of time to generate a netlist is small in comparison to the overall ASIC design schedule. Verification (i.e. test bench generation) makes up most of the ASIC design schedules I put together. Verilog's C-like structure provides a very flexible environment which integrates very smoothly into most test bench solutions. In addition, focusing on test benches illuminates one of Verilog's best features: the Programming Language Interface (PLI). I don't believe VHDL provides a PLI counterpart. Without a PLI many of the third party tools that I rely on, such as Signalscan, would not be available. At GI we have made use of Verilog's PLI for many tasks ranging from memory efficient input stimulus handling to automated test vector generation.

Experience questions Quite a number of VHDL proponents raised the issue that the VHDL contestants might not be experienced with the tools they had at hand or in ASIC design itself. (No one questioned the experience of the Verilog contestants because all but one got to gates.)

The VHDL contestants used Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys for synthesis and had a choice of Cadence and Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys for VHDL. (See Table 1) The nine Verilog contestants had comparable tool and ASIC design experience. One notable exception was Howard Landman of HaL Computers, with fifteen years experience as a CAD manager. Although Landman has never designed an ASIC, using Verilog, he was able to take third place in the design competion.

Fairness Of those 44 (16 percent) engineers who commented on fairness, six (2 percent) (all VHDL-only's) felt the contest was "rigged" in Verilog's favor (because they felt it was too low level) while the remaining 38 (14 percent) overall designers saw it as honorable.

Richard Schmidt; Exabyte ­ Even before I read the "Closing Arguments to the Jury..." I was thinking that this design contest was perfect because it showed exactly what engineers are up against ­ tools are late, support is incomplete and/or inexact, workstations crash inexplicably, testing is incomplete, etc. The only thing missing was a change in the specification 10 minutes before the end of the contest. Cool contest ­ thanks for all the work.

Two engineers felt that Steve Golson should have won because his design met the design spec while Larry's didn't ­ but this error wasn't caught by the faulty test suite.

Michael Fitzsimmons; Motorola ­ Steve Golson is the winner. Clearly stated in the spec.: "11" - Q holds state. The inability of your testbench designers to adequately test the design should not be held against Steve (or should I say assist Larry). The bottom line must be that the design is functionally accurate.

Type wars The most controversial topic was whether strong typing is a good thing or a bad thing. Some VHDL-proponents felt it was VHDL's core strength, while other VHDL-proponents saw strong typing as an incredible annoyance! Those who knew VHDtrong opinions on this. Of the bilinguals, 19 (29 percent) hated strong typing, six (9 percent) loved it, six (9 percent) noted it but couldn't decide. Of the VHDL-onlys, the breakout was 13 (15 percent) hate, 17 (19 percent) love, 10 (11 percent) noted but couldn't decide. Of Verilog-onlys and unknowns, seven (5 percent) hated, four (3 percent) loved, six (4 percent) noted but couldn't decide.

Steve McChrystal; Siemens Components Inc. ­ I thought the contest was a good one and I'm not seriously surprised by the results. I think the difference is in the nature of the languagethe languages, particularly the strong typing of VHDL, which at least one of your entrants had trouble with. VHDL forces you to think carefully about datatypes; if the design is simple logic, then this is a liability in terms of quick design time. VHDL has a better chance of producing a correct design if there is a mix of signal types, because you are forced to make sure they all convert correctly. C++ versus C is an analogy, the strong class binding of C++ objects can make for extra work up front making sure the types match up. In the long run, the design is more robust and easier to maintain because of it. I'm an IC designer who has used both - I'd use either one in real life, but I think Verilog has the edge in quick draw contests.

Iowa State University It appears that the Design Contest's results have even been verified by academia. What I liked about this unintentional validation is that it's not 90 minutes. That is, there was all sorts of time for the designers to do what they wanted. (I've received over 100 letters total starting with: "Your results didn't surprize me one bit!" If they were VHDL oriented I got explanations that VHDL tools took longer to run, VHDL was more verbose, and needed more initial time to get results. If they were Verilog oriented, I got explanations that Verilog was essentially C with wires, registers, built in flexible HW data types, concurrency and "it should naturally win.")

Jeff Echtenkamp; Iowa State University ­ Actually, an interesting look at VHDL vs. Verilog was accidentally done in our graduate level logic synthesis course. We recently got Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Design Compiler, Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys VHDL and Cadence Verilog-XL. While The rest of the class did their projects in VHDL, my lab partner and I did ours in Verilog. (We learned Verilog on our own; unlike my VHDL classmates, we had no class lectures, no T/A help, no professorial help.)

The results of this were overwhelmingly in favor of Verilog as a tool to teach HDLs. Our final project, a 75 kgate, 35 ns RISC processor was ~25 pages of Verilog. The VHDL people all ended up rushing near the end to just make something which worked and could be synthesized. Several groups failed at this altogether! (Whereas our project grew so large in functionality, our only problem was finding a workstation which had enough memory to handle the synthesis of the top level design.)

The general comments in talking to the other students was they spent a majority of their time fighting VHDL/ Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys . We spent a majority of our time doing design work, and optimization.

Bilingual judgments The opinions I value the most are those of the bi-linguals because they know both sides of the story. Of the bilinguals, 39 (59 percent) personally preferred Verilog overall, 16 (24 percent) were HDL neutral, six (9 percent) personally preferred VHDL, and five (8 percent) didn't comment on this.

Subhodip Ghosh; Western Digital Corp. ­ My transition from VHDL to Verilog came about two years back when I worked on a design which was about 45 kgates. I learned Verilog as the ASIC Vendor we worked with was only comfortable doing a final signoff in Verilog rather than VHDL. With the flavor of both the languages, here are my comments:

1. VHDL is a good structured HIGH level language but I feel Verilog is closer to actual hardware which is being designed.
2. As far as behavioral goes, I rank VHDL at par with Verilog, but when it comes to RTL, I consider Verilog has the edge over VHDL as far as the time to market ( i.e. meeting the design schedule is concerned.)

As far as the contest goes, I think Verilog has again proved the point. Yes, with VHDL you can achieve the same target but at the cost of design time and support. In the present industry, time to market of a product is the key to success. If a particular market window is missed, the ASIC and the man-months spent on it are a sheer waste. I strongly feel that given the choice and the design time I would opt for Verilog.

Don't shoot the messenger! I'd like to close with the observation that this design contest wasn't designed to be a referendum on Verilog vs. VHDL, but it accidentally became this. I was swamped with e-mail from both the Verilog and VHDL camps both saying that Verilog won in this contest. Judging the contest overall 175 (64%) felt "Verilog won", 16 (6%) felt "VHDL won", 48 (18%) felt "inconclusive" and 36 (13%) never voted! Along party lines, 70 (92%) Verilog-onlys voted "Verilog won" and 39 (44%) VHDL-only's did either an "inconclusive" or "no vote."

Jim Levie; Northrop Grumman ­ I am in the defense industry, and therefore we went right to VHDL when we switched to designing ASICs using HDLs. I have never learned Verilog. I have always thought the extremely tight typing in VHDL caused a lot of inefficiencies, and my guess is that this had a major effect in the contest results. Your contest seemed very fair to me. I would call Verilog the obvious winner.

Last word Yes, quite a few VHDL-only EDA companies like Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys , Mentor , Zycad, IKOS, Model Tech , and ViewLogic have suddenly been working to either buy or develop Verilog products for their customers. I don't see them leaving the VHDL business, though. In my own consulting practice I've just finished a Verilog ASIC for one customer and am now writing VHDL training material for another. For the next few years I feel being fully Verilog/VHDL bilingual, just like most EDA companies, is the wave of the future.

From his sheep farm, John Cooley founded & runs the outlaw E-mail Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Users Group (ESNUG), is president of the Users Society for Electronic Design Automation (USE/DA), and is an outspoken contract ASIC/FPGA/EDA designer. He can be contacted at "jcooley@world.std.com" (preferred) or (508) 429-4357 and loves hearing from fellow engineers.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  September 1995