Semiconductor

Give Me ASCII Or Give Me...

ASCII output for a simulator tool allows engineers to solve a cache RAM yield problem.

By Michael L. Longwell, William D. Atwell Jr., and Clyde H. Browning

ASCII output from a SPICE simulator provided an opportunity for the integrated circuit design team in Motorola's RISC Operation Design Group (Austin, TX) to write a useful software tool. We in the IC design team used that tool to solve a serious yield problem for the MC88200 cache memory circuit, which is used with the MC88100 microprocessor. This article should provide encouragement for software tool developers to use unencoded data formats.

Our group supports product transition from research and development to manufacturing. We are responsible for correcting logic errors that slip by the original designers, and also for improving the manufacturability of RISC products. We were given a challenging design job when the product and test engineers informed us that the MC88200 could not be built across the entire manufacturing process window.

For slow transistors (high threshold voltages or gate lengths), an enable pulse was too short for the content addressable memory (CAM) which it was designed to control. For fast transistors (low threshold voltages or gate lengths) the cache RAM exhibited a consistent pattern of bit failures. After increasing the pulse length in the CAM control circuit, we set out to solve the cache yield problem. The cache problem which affected the high-speed, high-price parts was an important business issue.

The MC88200 cache design relied on a static RAM developed for a less aggressive technology, but over the years, technological improvements seemed to allow the RAM to migrate to the present submicron process.

The RAM is arranged in clusters of 8 4-transistor bit-cells. Figure 1 is a schematic of an 8 RAM bit cluster, including lumped parasitic ground resistances.

All transistors in our RAM bit-cells are n-channel devices. Each bit-cell has a bit and a bit-bar storage node. The bit-cells have load resistors to pull up the drains of cross coupled pull-downs which are connected to bit and bit-bar lines by coupler (transfer) gates. The load resistors are designed to compensate for reverse-biased diode leakage current, but are insignificant when compared to the other circuit elements. The transistors all have the same channel length. Coupler gate widths are equal, as are pull-down gate widths. For bit-cell stability, the coupler gate width is about one-third that of the pull-down gate width.

RAM bits are designed to be written and read. To write a logic 1 into a bit-cell, the bit-bar line is driven low while the bit line and the row select line are driven high. The low level on the bit-bar line is transferred into the cell to turn off the bit side pull-down. After the bit pull-down is turned off, the high level from the bit line is transferred into the cell to turn on the bit-bar pull-down. Reversing the levels on the bit and bit-bar lines results in storage of a logic 0 into a bit-cell.

The read operation starts by pre-charging the bit and bit-bar lines (in our case to an n-channel transistor threshold drop below the positive supply voltage). Driving the row select line high allows the bit-cell to impart a differential voltage on the bit and bit-bar lines. A differential input sense amplifier is used to detect the value presented on the bit and the bit-bar lines by the RAM bit-cell. The three-to-one ratio of the width of the internal pull-down to the width of the coupler should prevent the pre-charge level from overwriting the contents of the RAM cell.

Figure 1. This schematic shows an 8 RAM bit cluster, including lumped parasitic ground resistances.

Layout of the 8 bit-cell cluster is given in Figure 2. This layout does not include the two polysilicon load resistors for each bit-cell. Load resistor drive strength was too insignificant to account for the yield loss. For the purpose of this article, we omit the shapes and fill colors associated with the pull-up resistors so that they will not obscure suspect circuitry. Analysis of the bit-cell layout led us to suspect sensitivities in the ground path which is routed in N+ diffusion through the cluster of cells. The ground diffusion is tied to metal on each end of the cluster.

Figure 2. Layout of eight MC88200 RAM cells. The layout of the eight bit cell cluster is more clearly understood here, excluding the shapes and fill colors associated with pull-up resistors.

According to bit-maps provided to us by product and test engineering, bit-8 of the 8 bit clusters would fail for parts with fast transistors. Low-supply voltages would prevent storage of a logic one in bit-8 when bit-7 stored a logic value of one. Drive strength of the load resistors was inadequate to improve the stored voltage in the RAM bits. We explained why only bit-8 failed on the basis of three symmetry issues. First, the middle cells in the cluster had nearly balanced ground path resistances. Second, only bit-1 has badly balanced ground resistance equivalent to bit-8 as shown in Figure 2. Third, an 8-degree implant angle used in manufacturing the silicon increased asymmetry of the bit-8 while it decreased asymmetry of bit-1.

After we finished brainstorming, we needed to model the problem. We found a SPICE-like simulation of the RAM that was written by the original RAM cell designers to model the speed of the circuit. It included a single ground resistance to model the speed of the middle cells of the 8 bit cluster. That simulation takes about an hour to run. It does not offer direct control of the voltage stored in the cells; rather, it relies on the accuracy of the modeling of extensive pulse generator logic for control of RAM timing.

We decided to develop a more controllable simulation model that would execute faster. We wanted to know the minimum stored voltage that represented a logic one in the RAM cell for various parasitic ground resistances and for combinations of process corner, supply voltage and temperature. We used a newer SPICE-like tool than the one in which the original simulation had been written. The newer tool provides ASCII outputs which are used as input for a graphical interface.

Simulation output took too long to review in the graphical interface. We rearranged the simulation to make the last line of the ASCII output indicate whether the RAM cell had passed or failed. Manual review of the ASCII output from the modified simulations was still too time consuming. We next wrote a C-shell script to review the results, adjust the voltage stored in the bit-cell then resubmit the simulation. In effect, the script performed a binary search until the minimum valid logic 1 voltage for a given resistance was known within a millivolt. We then extended the C-shell script to vary resistance, process, supply voltage and temperature. In all, the analysis required more than 50,000 SPICE-like simulations. We rearranged the data generated by the script to be compatible with the graphical interface for the simulator.

Figure 3. The graph shows the simulated relationships between the minimum valid stored voltage and parasitic ground resistance.

Simulation results show that fast transistors cause the problem to be worse. Since this agreed with the information provided to us by product and test engineering, we believed that our model was valid. Figure 3 shows simulated relationships between the minimum valid stored voltage and parasitic ground resistance for the original model as well as four modifications to that model. The relationship for the original model (marked "Orig." in Figure 3) shows that parasitic n+ diffusion ground resistances of more than about 575 ohms renders the bit-8 unstable. Process information indicated that in light of our simulation results, cache timing changes would not solve the yield problem. Our search for a solution to the yield problem moved from cache control logic toward the RAM bit cluster itself. After finding the ground resistance which would break our RAM model, we ran a sensitivity analysis on the sizes of the 4 transistors in the cell.

Figure 4. The ratio of good dies divided by EZ-functional dies is the percentage of dies passing functional tests at room temperature and nominal voltage.

Three of the solutions provided only minor improvements to ground resistance sensitivity. Increasing the width of the bit coupler ("bc" in Figure 3) improved immunity by about fifty ohms. Reducing the bit pull-down ("bpd") or increasing the bit-bar pull-down ("bbpd") only improved the immunity to ground resistance by about 25 ohms.

Reducing the width of the bit-bar coupler ("bbc" in Figure 3) improved immunity by about 150 ohms.

We modified the ground resistance in the original simulation of the 8 RAM bit cluster to validate our new model. We researched other products which were built in the same manufacturing facility as the MC88200. Of the products which contained similar n-channel transistor processing, several contained gate widths as narrow as our proposed bit-bar coupler width. From a design perspective, it was quite satisfying to find a solution which required only the n+ processing step of the MC88200 to change.

We needed a metric to represent our degree of success, and we settled on the ability to ship more product from the same amount of starting material. Figure 4 plots the ratio of good dies (i.e. the percentage of unpackaged parts which pass the complete production test) divided by EZ-functional dies (i.e. the percentage of dies passing functional tests at room temperature and nominal voltage). In addition, the plot shows the average ratio before and after the design revision. We believe that this ratio best indicates how well the design fits the manufacturing environment.

In our engineering environment, it is generally accepted that if a product yields significantly more EZ-functional parts than good unpackaged parts from a given amount of material started, the design is not robust. This means that the design does not yield well across the full range of possible manufacturing variations. Certainly, there are other issues that impact parametric yield, but this time we were able to identify and address a design weakness. Figure 4 indicates that after the design revision, the average percentage of good units from the EZ-functional set of units increased from 68 to 92 percent. Although this chart does not show it, there was no reduction in EZ-functional yield. Overall product yield increased by approximately 35 percent. Needless to say, this effort was perceived as a complete success by engineering and manufacturing.

ASCII output from a Motorola SPICE-like tool had enabled us to solve a yield problem for the MC88200 and MC88204 cache RAM parts. We used bit-maps of cache failures in developing SPICE-like RAM models. We wrote a C-shell script to build and submit simulations of RAM bit instability due to parasitic resistance. Simulation results were validated by modifications of a SPICE-like model of the RAM developed by the original designers. According to both simulation models, imbalancing the transistor sizes in process sensitive RAM cells would compensate for parasitic ground resistance without degrading cache performance. An example of this type of solution is described in U.S. patent #5,363,328 by Browning et al . (highly stable asymmetric SRMA cell).

Production silicon no longer exhibits cache sensitivity for the MC88200 and MC88204. From a business perspective, manufacturing costs for the products were reduced. From a design perspective, we developed a software tool to solve a challenging yield problem with a single manufacturing process step change.

Tool vendors can help designers do better work by providing ASCII outputs that allow creation of one-time solutions to uncommon problems.

Michael L. Longwell is a RISC operation designer. William D. Atwell Jr. is the operation design manager, and Clyde H. Browning is also a RISC operation designer. All work for Motorola in Austin, Texas.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.