Delving Into Deep Submicron

As technologies shrink, physical design has started to drive the design flow.

By Donald Smith

Semiconductor devices based on manufacturing process geometries well below 1µm (micron) offer the promise of fast, highly integrated designs, but they also provide a number of new challenges. These challenges result from shrinking device geometries, increasing numbers of transistors per die, faster system performance, and the need to minimize power consumption.

The challenges of submicron design begin at 0.8µm minimum feature size, grow at 0.5µm, and become excruciating at 0.35µm. The problems are exacerbated at higher speeds and gate counts. At 1µm, designers could enjoy the luxury of top-down design and synthesize nearly everything. "For deep submicron, such as at 0.35µm, the major challenge is in physical implementation of the circuits," says Mike Tsai, executive vice president of ArcSys Inc. (Sunnyvale, CA). "Therefore, the most important paradigm shift is that the layout optimization or physical design is equal to if not more important than the gate optimization. This shift of emphasis has significant impact to both design methodology and IC design automation."

For all designs, the objective is to implement the functionality, which is typically defined in a hardware description language (HDL), and the physical specifications, which are defined in top-level constraints such as die size, clock rate, power consumption, and noise margin. As shown in Figure 1(a), the conventional design methodology translates HDL to gate-level netlists. Since the gate-level designs implement the functionality and determine the major physical design results, conventional design methodology can be used for non-critical designs, such as at 1.0µm.

In the deep submicron era, the gate-level netlists still implement the functions. However, the physical design results, such as die size, performance, power consumption, and crosstalk, are largely determined by the layout of the designs. In this situation, conventional design methodology breaks down, as is evidenced by the large number of iterations experienced by designers. The major change in the new design methodology, shown in Figure 1(b), is the necessity to significantly increase the physical design emphasis in the whole design process.

Deep submicron issues are clearly on the minds of ASIC designers. "The two major issues that dominate current deep submicron design are timing and power," says Dr. Vassilios Gerousis, member of the technical staff of Motorola (Mesa, AZ). "In the timing domain, wiring delays and slew rate are the primary factors for 0.5µm ASICs." Figure 2 shows graphically that interconnect delay has become much more important than gate delay, as process technology has moved from 2.0µm to 0.5µm. For designers to accurately predict wiring delays and avoid endless iterations, Gerousis says that "floorplanning is becoming a requirement."

The challenges of deep submicron technology make it virtually impossible for design engineers to toss designs over the wall to the ASIC vendor. Because of the complex timing issues that must be resolved to get the design to work in silicon, the ASIC vendor is likely to toss it right back. "One of the biggest concerns with large, fast chips is finding a way to minimize the number of loops between generating the database with the netlist and having a layout that meets the required timing," says John Harrington, ASIC design department head at AT&T Microelectronics (Allentown, PA). Harrington says that he would like to get the design process down to one major loop with only one minor subsequent iteration if it's necessary.

To achieve that goal, you have to consider physical design all the way through the design process, acording to T.C. Lee, vice president of engineering for Silicon Valley Research (formerly Silvar-Lisco, Mountain View, CA). "Front-end floorplanning becomes critical at 0.5µm," says Todd Scott, manager of product development for ASIC product marketing at LSI Logic Corp. (Milpitas, CA). "The benefits include faster timing convergence when used with direct synthesis-to-layout capability, higher performance for critical blocks when implemented in conjunction with structured layout, and a closer match between logical design hierarchy and physical layout."

Timing issues There are four components of delay to take into consideration, according to Bob Wiederhold, executive vice president and chief operating officer at High Level Design Systems (HLD, Santa Clara, CA). These are slew delay (Ds), intrinsic delay (Di), transition delay (Dt), and interconnect delay (Dc). While a full discussion of delay effects would take all four of these parameters into consideration, here we will concentrate simply on gate delay and interconnect delay. Roughly speaking, gate delay consists of Ds + Di, and interconnect delay consists of Dt + Dc.

Transistors have shrunk much faster than metal lines. The upshot is smaller and smaller transistors driving relatively larger and longer metal lines. The most important effect is the interconnect delay dominating gate delay, as shown in Figure 2. Moreover, with smaller transistor sizes and longer metal lines, the percentage of nets within 20 percent of the typical delay value decreases, as shown in Figure 3. At 1.0µm, a statistical wire load model was satisfactory since 80 percent of the nets were within 20 percent of the typical delay value. But at 0.35µm, statistical wire load model assumptions are inaccurate for 80 percent of the nets. Because of this, most designers and foundries are turning to distributed resistance/capacitance or piece-wise linear models of wiring on ICs.

Crosstalk issues As we head toward 0.25µm technology, Motorola's Gerousis says, timing and power will remain the dominant factors. He notes that additional factors will become important. It will be necessary to perform better wire extraction and modeling to account for coupling effects between wires on the same layer and between layers. As coupling increases, crosstalk becomes dominant. Crosstalk not only affects signal integrity on the ASIC chip, but also introduces additional delay to the interconnect.

Long parallel metal interconnect traces can cause a crosstalk problem on some signals in submicron devices. "The lines are closer together and may be located in upper metal levels further away from the substrate voltage plane causing potential crosstalk problems," says Todd Scott. "Clocks, reset lines, and other signals that directly affect or change the state of memory elements are the primary concern. Crosstalk is prevented from occurring by 3-D modeling and by a correct-by-construction EDA methodology," Scott says. In essence, the layout tool monitors trace length and will allow parallel traces only the maximum allowed by design rules.

Clock traces pose special problems. Scott says that "for maximum performance and minimum power dissipation, it is best to locate the clock lines in the highest level of interconnect to minimize substrate capacitance. It is in this location, however, where crosstalk is most prevalent."

Power issues Power issues begin to dominate at 0.35µm. "At 0.35µm, 2 million gates plus 4 million bits of memory are possible on a single ASIC," predicts Scott. Enormous current distribution and power dissipation issues can result from such chips. Assuming the same power per gate per MHz (0.8mW/gate/MHz), such a chip would consume over 280W. "Managing the current distribution is achievable once the process design rules are established for eliminating electromigration concerns and controlling maximum power supply drops and ground rises," says Scott.

A design of 500k-gates at 140MHz, 5V, 0.5µm uses about 10 Watts as typical power consumption. The simplest way to reduce power is to reduce voltage supply. Since switching power is proportional to V2 by moving to a 3V power supply, the chip can reduce more than 50 percent of the power.

Designers can minimize overall power consumption through floorplanning for minimum clock distribution trace lengths and low voltage swing I/O usage. Power can also be minimized by using high speed serial I/O in place of wide parallel buses running chip to chip or over backplanes, according to LSI's Scott. For performance reasons, it is sometimes necessary to require board-level power removal techniques, such as heat sinks.

To address power consumption, "the designer needs to identify macros or blocks that consume the most power," says Gerousis. "He or she can use clock gating and other techniques to reduce average power consumption. Designers can replace high drive cells in non-critical paths with lower drive cells."

The bottleneck in performance is usually the datapath and the carry chain on the datapath, says Isadore Katz, vice president of marketing at Meta-Software Inc. (Campbell, CA). "You have got to switch over to datapath generators or datapath assemblers to do some of the work," Katz says, "and you have got to start to incorporate other logic styles."

Deep submicron solutions: reducing iterations The biggest challenge today is "making 'one-iteration' design flow really work," says John Harrington. This means that ASIC vendors, CAD vendors, and customers have to work closely to develop best methods, guidelines, and practices.

According to Mike Tsai of ArcSys, to support the new requirements of deep submicron designs, the new methodology requires three key elements: constraint-driven place and route, physical design constraints, and global place and route planning during synthesis. With this new method, designers can achieve the highest performance designs without time consuming iterations.

Constraints Placement and routing have always been the key to IC design automation. The recent progress in quadratic algorithms for placement and concurrent area routing has aided in solving highly complex designs with optimal die sizes. In addition, the timing-driven place and route algorithms have provided a means of accommodating complete timing information from the gate-level designs. As shown in Figure 1(b), this enables the new methodology to consider gate-level physical design constraints. With constraint-driven place and route, it is feasible to translate top-level constraints to more detailed gate-level constraints for placement and routing. Similarly, power and noise constraints considered during placement and routing define gate-level constants for power and noise immunity.

In conventional design methodology, layout designers try to understand top-level constraints, then manually influence the tools to achieve these constraints. The techniques they use include grouping of gates, pre-placement, and pre-routing. With the high complexity and emphasis on interconnect optimization in deep submicron design, the conventional method breaks down. The advanced algorithms for constraint-driven place and route enable designers to provide physical design constraints to drive the place and route tools. For example, compact-SDF can represent complete pin-to-pin delay information to place and route tools to meet top-level clock rate requirements. Physical design exchange format (PDEF) represents the necessary clustering of gates for placement purposes to meet the global delay constraints. Just as gate-level netlists implement the functions in HDL, physical design constraints drive the detailed placement and routing tools to implement a design that meets the top-level constraints. Power and crosstalk constraints are also part of the physical design constraints.

Global place and route planning during logic synthesis Due to the criticality of the layout, consideration of the layout has to be elevated to a higher level than before. Logic synthesis was successful in the translation of HDL to gate-level netlists; however, gate-level netlists are not sufficient in the deep submicron era. Top-level design constraints have to be translated to gate-level constraints, as stated above. To accomplish this goal, placement and routing must be performed on a global level to derive the correct gate-level constraints. Most conventional floorplanners attempt to solve some of the problems by manually transferring top-level constraints to a format that can be used by place and route tools, but a global place and route planning tool with synthesis can generate well-defined gate-level constraints. These constraints can then drive advanced constraint-driven place and route tools to meet top-level constraints. Furthermore, this global place and route planning tool should be consistent with the gate-level place and route tools to optimize the design. Therefore, global place and route tools must utilize algorithms consistent with those used by the gate-level place and route tools for the whole flow to work.

Deep submicron designs require layout optimization at various levels. The advanced design methodology for accomplishing layout optimization is a consistent solution for constraint-driven place and route, physical design constraints, and global place and route planning tools. "After talking to many designers, we have seen this methodology emerge as the most promising. Some of our customers already use the next generation tools to do their deep submicron designs," said Mike Tsai.

Other EDA vendors agree with this approach. They foresee different skills being required for designers in the future. "More and more designs will be done by the system designers, working at a very high level, perhaps behavioral. The physical design tools will automatically take care of the submicron details. As back-end tools become more sophisticated in handling these effects, designers should be completely shielded from them," says Cascade's Rousseau.

Todd Scott at LSI Logic agrees with the vision of powerful EDA tools shielding designers from submicron effects. "Most physical deep submicron design problems should be managed through improvements in the design tools. Due to increasing levels of integration, design engineers must develop the capability to manage the design process from higher levels of abstraction relying on EDA vendors to automate the process."

The main problem areas include dealing with interconnect delays, crosstalk, and power dissipation. There is wide agreement that designers should employ front-end global planning tools to allow for silicon level optimization.

Developing deep submicron ASICs and structured custom ICs with high gate counts and speeds above 100MHz will require new approaches in design methodology, new EDA tools, new methods of using the tools, and of course, very talented design teams. Next- generation tools are starting to emerge that promise a new methodology for deep submicron designs. *

Donald Smith is a freelance writer. He has worked for AMD, Intel, and Teradyne and is a test engineering consultant with Bay Networks.

integrated system design  February 1995