Semiconductor

Low-Power: An Overview

The convergence of trends leads to increased requirements for low-power circuits.

By R.T. "Tets" Maniwa

One source of many great struggles in human history has been the quest for power. People who don't have it want it; people who have some want more. Why should computer systems be any different?

Integrated circuits and computer systems are growing increasingly complex. To cope, designers will need to add power consumption to their list of primary specifications. Low-power is defined as logic circuits with an operating power of less than 1.3µW/gate/MHz, or analog circuits with operating powers of less than 5mW. This article will address some of the issues and trends of low-power circuits and systems.

Systems designers need to become more aware of the trade-offs and requirements for low-power circuits. Among the reasons power consumption is becoming more important to overall systems designs are the historical trends in the electronics industry. These trends have always been towards smaller, lighter, and higher functional densities in the final products. The current additional requirements in many product areas are wireless and portable operation, making the design task considerably more difficult from the power perspective. The desired capabilities for battery-operated products are days of use on a single charge or set of batteries, as in the ubiquitous Walkman-type tape players or cellular phones.

In addition, new requirements for lower power are being legislated into effect as evidenced by the Environmental Protection Agency's Green Computer program. All government purchases of desktop computers must meet the requirements that a passive computer operate on less than 30 Watts. Joe Barta, marketing manager of mobile products at VLSI Technology (San Jose, CA), sees a trend towards "deep green" computers on desk tops. These machines will suspend all operations until activity is required, then will resume operations in full power mode. This is similar to the power conservation modes of the laptop units.

ARPA is conducting research into these areas of low-power electronics to try to develop a mainstream technology base enabling a new class of electronic systems that dissipate less than one percent of the power of current systems. They feel that it will be necessary to balance and coordinate advances in the individually addressable areas of advanced materials technology, device technology, circuit architecture, power management, and applications demonstrations. These areas are particularly important in the areas of mobile computing and communications systems involving mixed-signal processing, radio frequency subsystems, and efficient power conversion and distribution systems of direct-current sources.

As circuit density doubles every few years, the problems of higher- power densities in ever smaller packages become harder to solve. Many designers are already aware of the difficulties posed by higher interconnect densities and fine line PCB geometries. Aydin Koc, vice president of ASIC Marketing at LSI Logic (Milpitas, CA), says that the operating power for a 100MHz, 200k-gate IC can be upwards of 30- to 40W. This power level is outpacing the capacity of the packages to dissipate the heat. The issues of thermal density and associated packaging constraints, as a result of the power dissipation in a system, are additional challenges for the designer, since high temperature operation is a primary cause for reliability and functionality problems within integrated circuits. Most reliability calculations model the failure mechanisms with a thermal coefficient in the exponential portion of the functions. The failure modes associated with temperature include active device failures and, along with current density, metal interconnect failures.

Figure 1. The ideal transfer function for a CMOS gate structure is compared to a normalized actual response for input voltage vs. output voltage, and for input voltage vs. supply current.

Low-power applications From an end-user perspective, low-power systems are very sensitive to power consumption. People are simply not happy when their battery-operated system shuts down in the middle of some important work.

Some of the latest portable computers now achieve a battery operating time of up to six hours for a 486-type machine. The size and weight limits for a truly portable computer allow no power for fans or other cooling components. The external packaging limits the size and weight of the battery packs, so increasing the battery size to extend operating life isn't always a viable option.

Cellular phones are another example of a low-power system. The most popular versions are the hand-held portable units. These pack a microcontroller for system control, analog, digital, and RF circuitry into a telephone handset-sized package that can supply up to a day's availability in "receive, stand-by" mode in addition to up to an hour of active talk-listen time on one battery charge.

Figure 2. This circuit represents a capacitive load driven by switched current sources, typical for any output structure.

In general, lower-power systems have to face additional performance constraints associated with the lower power. Unfortunately, designers no longer have the luxury of designing systems for performance without including the power consumption as one of the specifications. The advances in semiconductor processing and circuit architecture have contributed to tremendous increases in component performance while keeping a lid on power consumption. Although many of the trade-offs are difficult, many solutions are available with the appropriate power control solutions, or innovative design solutions.

Two effects generally occur when reducing supply voltages. First, the smaller power available dictates lower speeds. For all other things being equal, less current is available to charge and discharge capacitances or to drive loads. Second, the lower available power translates to lower output power or smaller signal swings. This can cause problems with noise and signal degradation.

Reasons for power consumptions The contributions to total power consumption are dependent on a number of variables: the base technology, packaging density, external environment, product performance, and supply voltages. In end-applications, higher speeds tend to require greater power, as shown in Figure 1.

The power dissipated in resistance, expressed as I ² R, occurs in both load devices and in parasitic elements. This set of losses will always be present to some extent in any technology, but is more noticeable in circuitry with resistive loads such as in analog circuits. With some of the deep submicron technology, the circuit parasitics such as lead (metal trace) and interlayer resistance can become a significant contributor to the static resistive losses, as well as requiring additional current in the dynamic losses.

When an active device is in its normal operating mode, it has a transfer curve and some I-V characteristics. The product of the voltage and current at the operating point is the power function and is present in all active devices. This is a fairly static value and includes leakage and biasing currents for the active and passive devices.

In CMOS circuits, the I-V transfer curve is ideally an instantaneous function that has a lossless transfer from one state to the other when the threshold is crossed. In reality, the transfer function is not as square as possible, so (potentially) large switching currents occur on each transition. In the theoretical worst case, the switching devices with zero internal resistance will be a direct short from supply to ground during the transition time.

In CMOS circuits, the greatest losses are from the charging and discharging of internal and external capacitances. This is most often exhibited as the specification of W/Hz per circuit element. The underlying mechanism for this loss is the energy required to charge and discharge the capacitance of the following gate or output load (including circuit packaging and PCB traces). Peak currents are derived from I = C( V/ T). Since the V is roughly the supply voltage for a CMOS circuit, T is the circuit rise or fall time, and C is the downstream load, the peak currents can be very large. The average switching power is P = C(V) ² F where C is the load capacitance presented to the output, V is the supply, and F is the switching frequency.

System costs for power consumptions A higher-power system will require larger power supplies than a low-power system. The additional costs for a larger power supply for the high power system can be substantial. The system areas affected include power supply busing, on-board bypass capacitors, backplane wiring, power line filters, and even the power cord and fuses. In addition, the larger capacity supplies will require more space than a smaller supply, possibly affecting the overall packaging.

The battery size, weight, and cost are functions of the total system power requirements and the desired operating time per charge. The battery costs generally increase with battery size. The size and weight of a spare battery pack and charger can be as much as that of the basic equipment, severely limiting the portability of the unit.

On-line power supplies can be rated on a dollars per Watt basis. The lower the total system power requirements, the less money you will need to spend on power supplies. The smaller power supplies also take less space and contribute less of their own power losses to the total system consumption.

The thermal management of a small electronic system requires many different capabilities which may not be readily available. The system may not have the space or power available to operate cooling components, while some may not tolerate the audible and electrical noise associated with active cooling components. Packaging constraints may force all the heat-generating components to be located in a small area, which exacerbates the heat flow problems. The user may not be comfortable with a hot plastic box on his lap. Openings in the cases which are necessary for cooling air flow may not be allowed for line-operated systems, especially for those systems going to Europe.

Other problems include the cost of fans and other cooling components, which increases with the amount of air needed to be moved. Heat sinks and heat pipes can help to move the heat from the source, but the heat must still be removed from the system.

The low-cost plastic packages cannot handle the very high power levels of high-integration ICs. This forces the ICs into more expensive packages with thermal management capabilities built in, or other more complicated cooling systems.

Low-power circuits The IC industry is addressing lower power systems in several ways. One way is that the industry is changing power supply operating voltages for digital components from 5V to 3.3V and analog components are changing from ±15V to a single 5V supply. These changes result from advances in silicon technology and in circuit architectures. Jeff Katz, vice president of marketing at Atmel (San Jose, CA), says that future trends will migrate digital supplies towards 2.5V, 1.8V, and even lower voltages. These supply voltages will be a multiple of 0.9V, the "end-of-life" for a battery cell. Device complexity, higher operating frequencies, and device physics drive the trends. The smaller devices, in the submicron geometries, have thinner oxides that cannot survive the voltage stresses of the higher voltage supplies.

Another way that ASIC vendors are addressing lower power systems is by having 3V core cells and macros for their products. Many of these have been optimized for operation at either 3V or 5V and have similar performance at the characterization voltages. They are retaining interface capabilities to 5V supplies with specialized interface cells. According to John Harrington, domestic OEM ASIC design department head at AT&T Bell Laboratories (Allentown, PA), one of the greatest impediments to faster change in supply voltages is the large installed base of 5V systems. These systems have requirements for backwards compatibility to other 5V (TTL) interfaces.

An alternative or a complementary strategy to power reduction would be to evaluate the need for raw speed in more areas of the system design and make appropriate changes in component selection where possible.

Some strategies could include:

• Reducing the operating voltages. This reduces power by 60 percent since the V is reduced from about 5V to 3V.
• Using smart power. Add intelligence to the system to anticipate, detect, and supply power only as needed. Some specific applications of this type of power control are evidenced in many laptop PCs and their power management features which only powers up active circuits and slows clocks when not needed.
• Working with slower clocks. This would contribute to lower power consumption, since the power in a CMOS circuit is a function of the switching speed.
• Limiting the input signal. In analog circuits, including A/D converter sections, bandwidth limiting the input signal can help in reducing the need for the highest speed circuits. This can also contribute by possibly allowing a lower digitizing rate in the A/D converters.
• Setting up I/O to not consume power when not operating. The trade-off is a longer transition time from the inactive state to an active one. Another side-effect is the extra leakage currents associated with the output stages floating to mid-supply and causing other output stages to be in the high leakage cross-over region of operation.
• Enlarging the output stages. For many ASICS the output stages are designed for an output drive capability of a standard IC. By sizing them to be large enough to drive the package and board parasitics plus some safety margin of fan-in loads, the size and power of the output stages can be reduced considerably.
• Switching to another technology. BiCMOS circuits have some of the best attributes of both the CMOS and bipolar devices with a trade-off of much higher processing complexity and consequently higher costs per IC. GaAs is another technology that promises lower power and higher speed devices. The technology has remained in a niche associated with high priced systems where speed is the primary design issue.

Semiconductor manufacturers are developing new designs and technologies to address some of the power use issues while maintaining the performance levels. The ultimate goal, says Dave Pivot, an applications engineer at Motorola Semiconductor (Phoenix, AZ), is circuitry operating on less than 1V. The final limits will be dictated by the physics of device processing that will limit the minimum size for a device. Low-power circuits are a field for research and investigation into ways to implement techniques and architectures that increase performance while decreasing power consumption.

Systems designers must accommodate the demands for higher performance within a limited power budget, in addition to meeting the basic system performance objectives, cost targets, and the time to market windows. The detailed work to carefully analyze the power budgets for all of the individual constituents of a system, unfortunately, is still left to the individual designer. The availability of new tools and techniques for optimizing power consumption will improve the situation and make life easier. Power tends to corrupt, and absolute power tends to corrupt absolutely, but insufficient power causes the system to go down. *

R. T. "Tets" Maniwa is technical editor of Integrated System Design. He has a BSEE from the University of California at Berkeley.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  March 1995