Semiconductor

An Alphabet Soup of Memory

Memory is more and more becoming a critical issue, and there is a plethora of acronymic devices on the market and in the wings. Here we take a look at the special function of memory devices and their primary characteristics.

By R.T. "Tets" Maniwa

The emergence of multimedia and video-intensive applications, as well as the ever increasing clock speeds in systems, has outpaced the abilities of standard dynamic random access memory (DRAM). RAM manufacturers have improved technologies and developed new architectures in response to this demand for higher memory speeds. This explosion of new RAM types will require careful analysis of the operating trade-offs among the various alternatives to make best use of capabilities of the new generation of memories.

DRAM has been the vehicle for advances in silicon processing, and one of the enabling factors in the proliferation of personal computers, video games, and graphical user interfaces. The advances in processing, unfortunately, have benefited the processors much more than the memories, to the extent that today's DRAMs cannot keep up with the requirements of the very high speed processors and graphic applications for data bandwidth and through-put. The many new types of RAM are all enhancements of the basic memory cell, whether a static with a 6T structure per cell or dynamic with a 1T structure. The changes in the interfaces and internal logic, as well as external organization allow the newer memory architectures to transfer the data to the system at much higher rates than the standard DRAMs.

Size and speed The issues that are driving the changes in the nature of memories are speed, size, power, organization, and cost. Most new memory applications require more speed and size while requiring decreases in cost and power per bit. This has led to a proliferation of new memory types which are trying to address the deficiencies of the current DRAMs. The now classic row address strobe/column address strobe (RAS/CAS) interface and x1 and x4 architectures impose severe limits on operating speeds. The propagation and access delays associated with the two stage memory access did not cause problems as long as computers were processor limited. A 100 MHz clock on a processor requires at least one data word every 10 ns, a data rate which standard DRAMs cannot easily achieve. "DRAM and SRAM are facing a major change in markets and technologies," says Cecil Conkle, senior product marketing manager for Memory Products, NEC Electronics Inc. (Mt. View, CA). "This is due to the timing limitations of the RAS/CAS."

The methods and speeds for addressing and accessing memory are also affected by the external organization. The granularity, the organization, and the amount of memory for the next increment of memory size, will change to reflect the increasing output width, from x1 and x4 to much wider outputs like x16, x32, and eventually x64 bits. This reduces the granularity to a more manageable increment in the neighborhood of a megabyte, with one to four packages for a memory increment, rather than the 16- or 64 Mbytes and 16 or 64 packages implied by a x1 architecture. Some people are forecasting that new RAMs in the 64 Mbytes and larger sizes will not be available in a x1 or x4 configuration because of the bandwidth and granularity issues.

Figure 1. The changes in processor and graphics bandwidth are compared to the changes in memory bandwidth over the same time. Graph courtesy of Rambus Inc.

The bandwidth of a device is defined as the product of the bus cycle time and the number of bits in the bus. One way to address the bandwidth issue is to increase the output bus width. The memory bandwidth is increased by the same multiple, since more bits are available in a single access. Another way to increase bandwidth is to increase the bus clock frequency. Many application-specific memories address this issue by changing from the derived RAS/CAS signaling to a synchronous mode where the system clock drives the timing requirements. This change in access reduces delays from 30 to 50 percent. Other internal modifications help to reduce other aspects of the propagation and access delays.

To truly meet the needs of the high bandwidth applications, memories not only need wider and faster interfaces, but also need to address the issue of latency. Many of the memories have been optimized for high throughput of relatively linear address ranges. "Most new RAMs focus on fast burst transfers, but have poor initial access times," says David Bondurant, director of marketing at Ramtron (Colorado Springs, CO).

"A high peak bandwidth, but long latency memory burdens the system designer with the need for higher than necessary clock rates, larger FIFOs, more power, and a more complex design," says Gary Banta, director of marketing at Mosys (San Jose, CA). "Designers should demand that every improvement in memory bandwidth be matched with an equivalent improvement in memory latency.

Cost and power The main drivers for the market are changing from the mainframe makers who had long product development and product life cycles and a fairly high tolerance for risk to the mass market PC people who are concerned about time-to-market, have fairly short design cycles, and are very risk adverse. "The driving issue is speed for Synchronous DRAM," says Bob Pierce ASIC manager at Oki Semiconductor (San Jose, CA). "Another issue is low power for the portable applications, and finally, the other major issue is cost."

Figure 2. This chart shows the various types of memory architectures and how they evolved to the current products.

The dynamic RAM and its variants are the determinants for low cost parts, since the DRAM has the smallest area on chip for each bit of memory. Multiple sources of high volume standard products set the baseline for price comparisons. According to Hank Ishihara, product marketing manager for memory at Hitachi America Semiconductor and Integrated Circuit Division (Brisbane, CA), "SDRAM is the memory type of choice for most of the applications because it is cost-effective on a per-bit cost basis, and because of wide availability from multiple vendors."

The design requirements for portable equipment are migrating to the desktop in the way of the "green" PCs and worldwide environmental rules for low-power operation. The higher density devices will need to go to lower supply voltages in order for the internal devices to survive. The very fine line geometries cannot withstand the voltage stresses of today's supplies. The beneficial result of the lower supplies is the very much reduced power consumption for the parts. Other aspects of wide, high-speed memories which translate to lower power are the smaller number of refresh cycles required, fewer chips needed to implement a given size of memory, and the fact that the memory may be on and off the bus much faster.

Specialty applications Although DRAMs are the high volume application, the static RAMs will see increasing use in cache applications, especially for Pentium class processors, which need a fairly large amount of high speed secondary cache to keep the instruction and data pipelines full for the very high speed processors. The synchronous parts, operated in a burst mode, are fully capable of supporting a 100MHz Pentium class processor with zero wait states.

Other very specialized memories are also available, but not necessarily as standard products. One specialty type is memory embedded in ASICs. This memory is used as RAM, ROM, scratchpad registers, and register files (very fast registers, less than 10ns). The embedded memories have many different implementations depending on final application. The embedded memories address many of the basic issues of size, power and speed by eliminating the package-board interface and very tightly couple the size and type of memory to the associated logic. The problem is the requirement for the rest of the ASIC to meet the performance and cost objectives.

A glossary of memory types

3DRAM -- Cache DRAM with on-board ALU for 3-D graphics functions. Burst EDO -- EDO plus a counter to transfer a linearly addresssed string of data. CDRAM -- Cache DRAM: internal SRAM cache added to DRAM. EDORAM -- Extended Data Out RAM, also called hyper page; a modification of fast page mode to hold data after CAS goes high, allowing faster CAS cycles. EDRAM -- Enhanced DRAM: very fast DRAM cells directly mapped to SRAM cache. Fast Page Mode -- a modification of the basic DRAM to allow multiple column accesses from a single row access. MDRAM -- Multibank DRAM, a collection of smaller, fast blocks of DRAM with on-chip interleaving, piplining. RDRAM -- RambusDRAM: specialized interface and 500MHz 8-bit wide bus controller plus on-chip interleaving. SBSRAM -- Sync Burst Static RAM: SSRAM plus a burst counter. SDRAM -- Synchronous DRAM: a standard DRAM with all functions referenced to the system clock, burst output mode. SGRAM -- Synchronous Graphics DRAM: an SDRAM with block write and write per bit. SRAM -- Static RAM. SSRAM -- Synchronous Static RAM: addition of clock to synchronize RAM to system clock. VRAM -- Video RAM: Dual Port or multi-port RAM. WDRAM -- Window DRAM, a modification of VRAM to reduce internal complexity.

Benefits and pitfalls The drive for more speed and density has enabled many products and technologies. The performance requirements of the systems and sub-systems in today's computers has exhausted the capabilities of the older standard DRAM. However, as the memory speeds and bandwidths increase, we will start to see a shift in computer memory organization from the current segmented main and video memories back to a unified structure, where the different types of memory are combined into one unit. This will allow better use of processor resources, simplify some parts of the memory controllers, and will minimize the memory boundary/granularity issues.

The virtual explosion of standards, pseudo-standards, and proprietary interfaces and organizations for the next generation of memories and the number of specialty memory products are attempts to provide solutions to the memory speed and access problems. This variety of parts can also cause sourcing and availability problems. The memory manufacturers must consider multiple supply voltages, output widths, packages, and unique product features for their memory lines. Therefore, not all of these memory products will be available at optimal price and delivery times.

George Robillard, director of memory products marketing at Fujitsu Microelectronics (San Jose, CA), suggests that designers look to the following issues when selecting memories:

(1) Follow the PC guys if you are looking for economical sources of memory. There are too many variations coming on line, so there will be a shake-out of parts.

(2) Be careful which parts get designed in, because niche architectures may not be in production in any volume (implying higher costs and/or greater difficulty in getting any parts for productions.) There are hundreds of options for memory variations. Feature selection will be difficult and critical. Watch which ones are most viable. Operating voltage, granularity, and other special features are important.

Cecil Conkle of NEC agrees, and in addition, notes that one should be aware of two further issues:

(1) The transition towards synchronous devices.

(2) Shifts from fast page to hyper page modes.

There is pressure to become more familiar with the directions and strategies of memory suppliers. Many changes are coming, most of which have good technical reasons for being. Try to keep aware of the major changes by keeping in touch with suppliers.

The latest generation of faster and wider memory parts will move the operating bottleneck from the memory back to the processor. The newest parts will enable high performance designs fully capable of meeting the requirements for multimedia and other memory bandwidth intensive applications.

The way you wear your hat,
The way you sip your tea,
The memory of all that--
No, no! They can't take that away from me!
Ira Gershwin; Shall We Dance? "They can't take that away from me"

Tets Maniwa is the technical editor for Integrated System Design .

Table 1
A summary of the important characteristics of the various RAM product types
Description	Advantages	Disadvantages
3DRAM	On-chip cache, on-board ALU, optimized for 3-D operations	Single source, non-standard, requires complex controller.
Burst EDO DRAM	Addition of burst counter allows fast output of a string of linear addresses.	High latency if next address is not linearly consecutive.
CDRAM	On-chip cache, separate address decoders for DRAM and Cache.	Requires special off-chip cache controller.
DRAM	Industry standard parts, low cost.	Becoming too slow for either main memory or video.
EDO DRAM	Uses "standard " interfacing, makes more of inherent internal speed available to user.	May not be fast enough without external interleaving.
EDRAM	SRAM substitute; static buffer and cache controller on chip.	Single source.
MDRAM	High through-put, low latency, fine granularity.	Single source, non-standard, requires complex controller.
RDRAM	High through-put, many suppliers.	Non-standard, requires a separate complex controller.
SBSRAM	Addition of burst counter allows fast output of a string of linear addresses.	Potential for high latency if the next address is not linearly consecutive.
SDRAM	JEDEC standards exist, much higher through-put than DRAM.	Not all parts meet standards.
SGRAM	JEDEC standards exist, superset of SDRAM, single-port.	Not all parts meet standards.
SRAM	High-speed parts with standard interface.	Low density, high price/bit.
SSRAM	Addition of logic allows sync with system clock, allows faster timing.	High cost, smaller memory sizes.
VRAM	Dual port, standard interface requirements.	High cost, extra functions may not be used.
WRAM	High-speed, dual-port; simpler interface than VRAM or RAMBUS.	Single source, non-standard

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