Special Report:
DAC Design Methodologies

Novel Design Methods Described at DAC '95

Design methodology boosting performances, cutting time-to-market, reducing circuit complexities and allowing concurrent design are the focus of the Designer Track at the 1995 Design Automation Conference.

by Jonah McLeod

Methodology is proving critical in the design of silicon chips with process rules of 0.5µm and smaller. It is so important that the 1995 Design Automation Conference, June 12-16 in San Francisco, CA, has devoted a new Designer Track to the topic. Four of the 41 sessions comprise the track. Session One details procedures used in the UltraSPARC microprocessor design from Sun Microsystems (Mountain View, CA). Session 14 contains three case studies detailing communications as well as microprocessor chips design practices. Advanced techniques in test generation, behavioral synthesis, and model checking are detailed in Session 18. Finally, Session 20 reveals concurrent engineering methods.

In describing approaches used in developing the UltraSPARC processor, author Marc Tremblay of Sun's SPARC Technology Business details a simulator the company created to model the complex chip's features. One rationale for developing the simulator, Tremblay states, is that non-blocking caches in the new UltraSPARC had to simulate with other processor elements, a capability commercially available simulation tools did not offer. Tremblay explains that a missed cached latency in a multiprocessor can be partially compensated by executing other independent instructions. Furthermore, he noted that interdependency among processor functions requires adjusting some features simultaneously to measure the impact on the total system.

Concurrent design played a major role in constructing the complex, high-performance UltraSPARC processor. In the session's second paper, Lawrence Yang and his associates at Sun's SPARC Technology Business explain the methodology used to develop both ASIC and board designs simultaneously. Furthermore, the paper details how functional validation, physical design, electrical design, and timing analysis of board and ASICs occurred concurrently. The authors also describe the processes used to consolidate information from all individual design efforts.

To ensure the complete system met a tight schedule, software development for the UltraSPARC also occurred in parallel with hardware design. James Gateley and his associates at Sun's SPARC Technology Business describe how emulation facilitated an early access to UltraSPARC processor functionality. Gateley says emulation shortened the design iterations between front-end design capture and back-end layout to achieve a successful design. Emulation also decreased the time to achieve a silicon testbed. Finally, emulation helped ferret out software bugs long before final silicon, thus greatly improving overall design quality.

A summary of CAD methodology used in the UltraSPARC design is the subject of the fourth paper in the session. Nigel Ross and others at Sun's SPARC Technology Business describe CAD flow strategy, tool development and integration strategy, and design infrastructure. The authors stress concurrent design style, modular CADflow environment, incremental design verification and early design quality checking. Early in the design process, Ross and his team undertook architectural modeling and performance evaluation to create a behavioral description. After completing the description, the team partitioned the design into structural units. Thereafter, the design moved into logic synthesis, simulation, and debug.

Figure 1. A methodology that allows architectural information and synthesis options to be stored in library elements.June 1995 Special Report

Shortening time-to-market Three case studies being presented in Session 15 of the DAC Designer Track illustrate the key role design methodology plays in shortening time-to-market. The first case describes the experience at Siemens AG in Vienna, Austria. Author Thomas Albrecht needed to simulate two redundant boards connected back to back.

Four Pentium processors, 28 ASICs (containing 2.4 million gates in total), 320 Mbytes of DRAM and several standard integrated circuits populated the two boards. The paper explains the contribution extensive configuration management tools made to controlling the complex project. Such management was essential since geographically dispersed teams used design tools from a number of different vendors. Furthermore, the author says concurrent development helped minimize total design time.

System simulation was started early in the process to test board functionality among the ASICs being designed and other borad components. System functionality was divided into 50 test cases. Each test case tested specific board functions. Expert engineers focused on a few specific test cases and handled them across the ASICs.

In a second case study Thorsten Groetker and others of Aachen University of Technology in Aachen, Germany, describe the system design of digital receivers and other digital signal processing. Two different tasks were undertaken, algorithm design and hardware architecture development.

The designers created a methodology comprising a VHDL generation program called ADEN and an extensible library of reusable components called COMBOX. It cooperates with a commercial data flow simulation system called COSSAP. In their design, the COMBOX library transferred a design captured during the algorithm development task into the architecture development task.

The technique complements high level synthesis in that architecture information and synthesis options can be stored in the library components. Any VHDL coding style and architecture type can be encapsulated in a library component. Algorithm design and hardware implementation is illustrated in Figure 1.

In the third case study, authors Charles H. Malley of Motorola and Max Dieudonne of IBM (both in Austin, TX) describe a logic verification methodology used in the PowerPC microprocessor design. The chip design the two described exceeds five million transistors. The approach is suitable for a large class of chip designs. It integrated several validation techniques into an automated logic verification strategy.

Three PowerPC microprocessors designed right the first time resulted from using this approach. The method combines formal verification techniques with a divide and conquer strategy to achieve comprehensive levels of logic verification in a reasonable time. By contrast, the conventional technique uses large amounts of event-driven gate- and switch-level simulation. It suffers slow performance, a small number of simulation cycles per second, and poor functional coverage.

Figure 1. A Model Based Test Generator allows test generation for different architectures via a heuristic database of testing knowledge and a model of the processor.

Coping with design complexity As integrated circuits allow upwards of four million transistors on a chip, designs become too complex to be handled manually. Designers must increasingly rely on automatic tools. In the first paper of the DAC Designer Track, Session 18, Aharon Aharon and others of the IBM Matam Advanced Research Center (Haifa, Israel), explain a new methodology and test generator used to verify six IBM PowerPC processors. As a result, only a fifth of the simulation cycles previously used on a RISC System 6000 chip progenitor of the PowerPC was needed to verify the six PowerPC chips.

An expert system at the heart of the test generator contains a heuristic data base of testing knowledge and a formal model of the processor architecture (see Figure 2). The tool derives its name, Model Based Test Generator, from the fact that the model can generate tests for different processor architecture. In operation, functional verification simulates a subset of possible tests. The tests execute in the HDL model and the results are compared with the architecture specification prediction.

In the second paper in the session, Yossi Malka and others from the IBM Matam Advanced Research Center describe another high level tool that generates circuits from a behavioral description. The synthesis-based design methodology performs high-level synthesis (HLS) of behavioral hardware-description language descriptions. HLS automatically schedules (assigns to states) operations and data transfers. By contrast, in register transfer language and logic level synthesis, the designer assigns operations and data transfers. In a square root function, for example, HLS automatically schedules all internal operations that compute the square root. It also selects the state in which to perform each multiplication, addition, etc.

The methodology presents three modes of scheduling I/O operations. One is cycle-fixed , in which the design has exactly the same cycle-level I/O timing before and after synthesis. A second mode, called superstate-fixed , comprises I/O operations falling between adjacent waits and in which post-synthesis timing behavior is a potentially stretched version of pre-synthesis timing. The third mode, called free-floating , imposes constraints on I/O scheduling between pairs of operations that share a common port and those explicitly supplied by the user.

Cycle-fixed and superstate modes establish rules for waits, loop boundaries, conditionals, and I/O operations. The rules differ only slightly between the superstate and cycle fixed modes. The free floating mode has no rules.

The third paper in the session provides an alternative approach to the conventional design flow: creating a system requirement and then proceeding from design specification to behavioral modeling and design synthesis. The methodology authors Massimo Bombana of Italtel (Milan, Italy) and his associates propose to allow a designer to conduct much more design exploration early in the design phases. The technique was used on a complex communications IC.

An application-oriented specification language for assuming properties and an abstraction algorithm that generates an intuitive and efficient representation of synchronous circuits is the topic of the fourth paper in the session. Jorg Bormann and others of Siemens AG (Munich, Germany) present the language, which is embedded in Siemens Circuit Verification Environment (CVE).

Bormann explains that current hardware design validation requires a significant effort. His paper presents an alternative to simulation to shorten the overall circuit development time. In the CVE approach, fully automatic symbolic model checking algorithms validate state machine properties. For example, they can prove absence of deadlocks, lifeness properties (something good will eventually happen), and safety properties (something bad will never happen). The specification langauge, CVE interval language (CIL) specify the properties to be checked.

Enabling concurrent design In Session 30 of the Designer Track, author Asim Smailagic and others, on the faculty of Carnegie Mellon University, state that, much like new software and hardware tools, design methodologies must be debugged and benchmarked so they can be compared and improved. To develop a benchmark that can be applied to different designs and design teams, the university developed six generic axes of design activity.

One is the number of designers in a team. A second is the number of CAD tools used during the design. A third is the total effort to complete the design in person months. A fourth is the number of artifacts created. A fifth is determining if the design is routine or innovative. Finally, the sixth is the complexity of the design. To test the benchmark, Smailagic and his team evaluated four designs of different wearable computers. The designs were performed at different times with different numbers of designers, tools, etc. The benchmark allowed the four to be compared and some conclusions drawn about which was the most effective.

In the second paper, authors Giovanni Mancini and Dave Yurach of Bell-Northern Research (Ottawa, Ontario, Canada), describe a methodology for hardware-software co-design and co-verification of a large ATM switch. The resulting switch contains hardware, embedded control software and system control software. Large ASICs implement the switch's functionality. Emulation on a hardware prototype developed before lab samples were available permitted concurrent development and verification of system software. One goal was to reduce system integration time and design iterations caused by system errors.

In the third paper of Session 30, author Allan Silburt and others at Bell-Northern Research, describe a methodology for concurrent hardware design and verification. Functional hardware verification spanned ASIC, board and system level design. It enables design simulation concurrent with ASIC and board development. The simulation strategy relies on on rapid development of behavioral models of ASICs to enable board design to proceed in parallel and to achieve simulation efficiencies.

The process provided early visibility of over 200 issues in the system of which 32 were critical to the successful conformance and timely completion of the project. Silburt and his team created an ATM switch. A minimal system consisted of two line interface modules and one switch (SM) module. On the boards were eight ASICs ranging in size from 20 to 80 kgates plus embedded RAM. The LIM contained six boards and a backplane. The most complex LIM board contained eight instances of four new ASICs. The SM contained four boards and a combination backplane-switch matrix. The most complex SM board contained 20 instances of two new ASICs.

Jonah McLeod is editor-in-chief of Integrated System Design .

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  June 1995