A Yen for Harmony An EDA standards conference in Japan provides food for thought with a look at different approaches to standardization. By Steven E. Schulz

Recently, I had the pleasure of participating in EIAJ's EDA Standards Forum '94, held at the Nippon Convention Center near Tokyo. The forum, now in its seventh year, drew over 150 Japanese managers, professors, and engineers together in an atmosphere of solidarity to focus on advancing EDA standards.

I was impressed by many things during my visit. Most notably by their graciousness and respect for tradition. I'm also fascinated by the latest "high-tech" electronic gadgets, which seems to be their obsession. As a token of their appreciation for speaking at the forum, I was given some fun gifts, like an automatic, battery-operated letter opener (don't laugh, it sure beats a Gut-be-Gone!). Or my favorite, a credit-card-sized, digital tuning, AM/FM radio with alarm clock, featuring pre-programmed station presets for every different listening area across Japan, including a special set of presets just for their train system.

But what impressed me most during my business there wasn't the latest electronic gizmo. It was their intense level of cooperation and commitment to each other's future. This was particularly evident with EDA technology, where the Japanese have clearly understood how important EDA tools are to their mutual objectives. They understand that, as they make their shift from internal toolsets to a mixture of third-party offerings, the status quo will not be good enough. They understand the power in numbers that results when 29 Japanese companies decide together that certain HDL methodologies of the past will not continue to serve them as well in the future. They are also recognizing that it's not just fab capacity that counts, but intellectual design content, aided by first-class design tools. They also understand that, in some respects, they are entering the commercial EDA arena later than many U.S. counterparts, most notably with VHDL. And they want to do it right.

For example, I was impressed with how the Japanese electronics companies that comprise EIAJ's HDL sub-committee seem to have decided, within the last 12 months, to accept and adopt VHDL (along with ongoing Verilog support, of course). This recent shift has come about partly in response to their own designers, who, according to a recent EIAJ survey, stated that 75 percent intend to use VHDL in the future. This group shift was also validated by the relatively heavy focus on VHDL-related issues throughout the conference, as well as by numerous conversations I held with their managers. Further, all this was consistent with another survey of Japanese trends presented at the forum by EDA industry consultant Ron Collett.

The Japanese do not intend to duplicate the growing pains of VHDL's early days in the U.S. and Europe, however. Rather, they plan to learn and adopt the best practices of today, but also actively promote their own priorities through a unified voice to standards bodies. The highest priority of EIAJ's HDL sub-committee is--not surprisingly--a "harmony" (i.e., interoperability) between VHDL and Verilog ASIC libraries. To be sure, there were several highly interactive panel sessions at the forum to address just this topic.

One highlight of the forum was a panel session on "HDL Futures." This session focused on HDL harmonization between VHDL and Verilog, with the highest importance being the need for a common ASIC library standard. This standard must include accurate timing, as well as a full verification suite. Although syntactic language convergence wouldn't be practical, there are ways to semantically bring the two environments together with well-defined mapping. Members of the panel seemed to agree that while SDF is a good common ground for timing, it's growth and evolution would be best nurtured under IEEE (the home of the VHDL, VITAL, and emerging Verilog standards).

Interest was so high at a special VHDL focus meeting that the attendees had to be moved to a larger room. I quickly learned that the Japanese have formed EIAJ working groups to parallel the structure of various IEEE VHDL working groups. As I listened to each working group chair present the status of their involvement from Japan, I could not help but be impressed. In a very short period of time, the Japanese have shifted from being (more or less) observers of VHDL to being participants.

Could we do the same thing in the U.S.? Possibly, but there are some risks and limitations inherent in adopting this "all or none" mindset. While we (i.e., "the American electronics companies") may take longer to arrive at consensus, we also don't get bogged down while waiting for agreement. This allows each of us to react as we see fit, taking advantage of an opportunity here and going out on a limb there. I think this works very well for the American electronics companies, particularly in the early stages of the game. Being more nimble has its advantages.

The problem lies with how we cooperate once we find ourselves all pretty much trucking down the same road, particularly when it comes to EDA. Too often, we realize that an existing methodology, capability, or need is no longer adding competitive value, yet we continue to pay the price of non-uniformity all too long. We can suffer like this for years before we seriously consider working as one industry. When the situation gets bad enough, then (and only then) do we cautiously band together to solve the problem. With better teamwork, we probably could've resolved the same problem before it got so costly and messy. There are many examples of this happening within EDA, including recent standards efforts like VITAL and OMF. We'll likely do it again when we get caught unprepared for the major shifts that EDA must make to support deep submicron.

So maybe we in the U.S. have something we can learn from the Japanese and the EDA Standards Forum after all, and yet retain the advantages we have always enjoyed from being headstrong, independent, and uniquely American. *

Contributing editor Steven E. Schulz, P.E., is a member of the technical staff at Texas Instruments (Dallas, Texas).

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integrated system design  February 1995