Editorial

Coping with Integrated Circuit Complexity Changes taking place in the industry keep things dynamic. As we cycle into spring, changes occur in nature, in the industry, and in the magazine. by Jonah McLeod

Today, integrated circuit technology has changed considerably, most notably in the nature of integrated circuit design and the methodology used to create these devices. Today, whole systems are being designed on a chip with complexities of several million transistors. This huge circuit population is forcing design creation and layout to overlap. Furthermore, clock frequencies in excess of 100MHz, a natural consequence of higher integration, are making digital circuits exhibit analog phenomenon.

To illustrate how design complexity has increased, we surveyed a thousand of you, our readers, in January of this year. We asked the average gate size of the ASICs you were designing. A large number, 20 percent, responded. We found the largest number, 40 percent, were building chips with 50 to 100 kgates, with only 26 percent doing devices of under 50 kgates. Another 27 percent were working with devices of 100 to 500 kgates, while seven percent of you were building chips with over 500 kgates.

These circuits are being designed in record time with few if any design iterations. One reason is the vastly reduced market windows confronting competing companies. Lew Platt, chairman and chief executive officer of Hewlett-Packard, stated at Design SuperCon '95 this March in Santa Clara, CA, that product life cycles are now 9 to 12 months long.

In such a highly charged market, product definition, prototype realization, and production volume occur with a minimum of iteration. Platt says that products at HP are designed entirely on computer and transferred to production electronically. Typically, the only design iteration occurs during the transfer from engineering to manufacturing, and it is done to make the device more manufacturable.

Design tools make all this possible and our January survey indicated that most readers were using such tools in their designs. In the survey, we found that 79 percent of you were describing circuits with high-level description languages, some using more than one HDL. Of this group, 58 percent were doing VHDL designs, 62 percent were designing in Verilog, and another 10 percent were using other languages.

Another major change wrought by the increased complexity accommodated on a single chip is the use of a new design methodology. On chips with a million gates or more, gate delays are inconsequential while interconnect delays have become the major constituent of overall circuit timing.

This complexity now makes it encumbent for system designers to understand and incorporate back-end layout during initial design creation. It has also created demand for accurate floorplanning tools that help system designers evaluate the affect layout has on a circuit. (Please see this month's Focus Report on physical design tools).

In closing you will notice that Lindsey Vereen, my predecessor on this page, is no longer here. We wish him well at his new endeavor. I plan to carry on his pursuit to increase the quality of Integrated System Design and I encourage you to let us know when we hit and miss the mark.

Jonah McLeod is editor-in-chief of Integrated System Design. He has been publisher and editor of Electronics magazine, and before that Systems & Software, Electronic Design, and Computer Design. In 1992, he received a Neal Award from the Business Publishers Associations for his editorials in Electronics. He has written books on logic synthesis, silicon compilation, and optical and magnetic storage systems.