Editorial

Will Datapath Compilation Be the Next Hit EDA Tool? When a new company headed by an old name resurrects an old technology, can success be far behind? by Jonah McLeod

In the last few years, the tool responsible for the greatest amount of designer productivity boost has been logic synthesis. Now, as integrated circuits are implemented in deep submicron design rules­0.5µm or smaller­another tool is needed to further increase productivity. That tool may well be the datapath compiler. One reason for the emergence of datapaths is the changing nature of computing needs for the average PC user.

The sea change occurring in the PC market is the advent of increased amounts of audio and video data types the computer is now processing. Such complex data types are compressed, sometimes encoded, and demand real-time processing. Such compute-intensive functions drive up the number of designs with large numbers of datapaths.

Logic synthesis is an ideal tool for creating and then minimizing combinatorial logic; however, it is not well suited to fabricating datapaths. In fact, when examining a netlist, synthesis tools identify language statements describing a datapath and replace the logic with an optimized macro that fits the description from a library of macro functions.

The problem in this approach is that the substituted macro is not an exact match for the circuit it replaces. Furthermore, once the function is instantiated in the netlist, the logic synthesizer cannot alter it to suit the original designer's intent. Thus, large parts of a complex designs are unalterable standard cells, surrounded by optimized combinatorial logic.

Another problem confronting the logic synthesis tool is that below 0.5µm, the interconnects account for a much greater amount of delay in the signal path than do logic gates. Logic synthesis tools now must radically change their timing models to accommodate this turnaround.

In addition, when the synthesis tool is creating the "glue logic" to connect major blocks such as a processor core with memory, state machine, etc., the designer must floorplan the design during design capture. This helps anticipate timing delays in the interconnect between these major blocks.

While the datapath compiler does not solve the problem confronting the logic synthesis tool, it addresses a problem heretofore ignored: datapath optimization. Moreover, the datapath tool solves the problem in the silicon and not only in the netlist.

The compiler will not only create an optimized netlist representation of the datapath, it synthesizes the silicon layout at the same time. In effect, this creates the equivalent of a customized hard macro on the fly.

This capability is not new. David Johannsen developed a technology called Bristle Blocks at Cal Tech in 1978. It was commercialized by Silicon Compiler Systems, which was later acquired by Mentor Graphics . VLSI Technology also developed a datapath compiler technology as did the tools group inside Cirrus Logic. The VLSI tool now resides at Compass Design.

The news is, recently, David Johannsen resurrected the datapath technology and formed a company, Silerity, to commercialize it. Last March, Silerity licensed the technology to Viewlogic for use in its synthesis product line. In addition, Mentor Graphics is also resurrecting its datapath technology, and I would not count Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys out of contention either.

Drama in this next tool battle surrounds whether one vendor will grab the lion's share of the market as Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys did with synthesis. Could Silerity emerge as the next Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys ? We'll see.

Jonah McLeod is the Editor-in-Chief of Integrated System Design.

integrated system design  July 1995