Editorial

Start-Up Promises to Breathe New Life Into Gate Arrays, Check It Out A technology to make gate arrays assilicon efficient as standard cells. by Jonah McLeod

I met with Faysal Sohail, director of marketing at Silicon Architects (Sunnyvale, CA). I wanted to know why Synopsys Inc. (Mountain View, CA) had recently acquired this start up.

The problem SiArc claims to solve is making gate array as silicon efficient as standard cell designs while preserving the time to market advantage gate arrays enjoy. In addition, Sohail says the solution also cuts power consumption in large ASIC designs.

SiArc's solution assumes sea-of-gates arrays use the same cell for both logic functions and drivers in critical paths, large fanout, and clock distribution.

SiArc's proprietary solution is a small compute cell and larger adjustable-size drive cell. The basic compute cell, optimized for memory and data path operations, comprises two N-type and two P-type transistors. Drive cells, optimized for performance in critical paths, comprise multiple N-type and P-type transistors concatenated to achieve the desired drive. Transistors are tightly spaced to achieve cell-based densities. Interconnect to configure the transistors into logic functions occurs in up to four metal layers.

SiArc's technology will be incorporated into Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys ' synthesis tool, with the largest installed user base. The library is synthesis-friendly. For example, it rids the need for inverters since the function is built into each gate. The synthesis tool also understands the multiple drive strength of the cells, thus it can configure each cell for exactly the amount of drive needed for its specific function. For example, only three compute cells and one drive cell are needed to build a flip-flop. If the flip-flop is driving a larger fanout, then adjust the drive cell for more drive current.

There are three elements to the company's solution: tools, library, and architecture. At the heart of this new offering is a patented silicon structure that ASIC vendors are licensing from the company. Vendors will also pay a royalty to SiArc for each chip shipped. SiArc reasons that the savings in silicon area will offset the royalty payment.

Beyond the silicon architecture, SiArc will provide a complete ASIC library for each ASIC vendor's process, 0.5 ým, 0.35 ým, etc. Included in the library are a set of silicon compilers, which also add value for both ASIC vendor and designer. There are 100 different compilers including RAM, data paths, and MSI logic functions, counters, timers, etc. With the compilation technology, it will eventually be possible for a designer to submit the algorithms for an MPEG chip, for example, and the compiler will automatically create an optimized data path to implement the function. The foundry can also embed core cells in the array just as with their own ASIC library.

Furthermore, unlike data paths found in data processing applications which are regular structures with uniform data path sizes, multiples of 8 bits, SiArc's data paths can be irregular, a mix of different widths. This provides a solution for communications and multimedia designs.

This capability offers a solution for a number of problems confronting designers of complex circuitry. It makes gate arrays competitive with cell-based designs. And if the company's claims about compilation capability rings true, some of the problems confronting designers building deep submicron designs will also be eased.

Jonah McLeod is editor-in-chief of Integrated System Design.

integrated system design  September 1995