Programmable Notes

And In This Corner... FPGA and CPLD proponents are turning up the marketing heat, but do users really care? by Larry Waller

Welcome to the hottest topic in programmables: complex PLDs versus FPGAs.

There are many solid marketing reasons for hard-selling proponents on both sides not to see eye-to-eye on this issue, of course, and their respective merits have always sparked lively debates. Lately, however, the rhetoric fired back and forth between CPLD and FPGA camps has been heating up to incendiary levels.

Consider the recent statements of John East, CEO of Actel Corp. (Sunnyvale, CA), who has emerged as the most outspoken FPGA advocate. "The demarcation between them has never been more clear," he says. East draws the dividing line at about 2k usable gates, the point at which most people say the differences start to become clear.

Before going on the attack, East ticks off a number of features for both devices with which even CPLD leader Altera Corp. (San Jose, CA) can mostly agree. Above 2 kgates, FPGAs have had it all to themselves, mostly because they look like tried-and-true masked gate arrays whose logic and interconnects can be programmed. East and other FPGA backers give CPLDs credit for designs needing fewer than the magic 2k figure, which amounts to an easy enough compliment, since the devices long ago grabbed a big share of these sockets. Altera and AMD, the two firms duking it out in CPLDs, certainly will take little issue with this.

Beyond the density dividing line, East has a far different--and harsher--view, offering the Altera MAX 7000 series as an example. Other FPGA backers generally say these things, but not publicly. According to East, not only does CPLD speed "fall off pretty fast, but in real applications, as opposed to PREP benchmarks, interconnect resources are no good. Moreover, they're not I/O friendly, there's too much delay, and power gets out of hand. I'm confident that above 2 kgates, we'll beat 'em all day long." The Actel executive sees FPGAs, both his antifuse line and others, keeping their sales lead over CPLDs through the end of the decade. East adds, however, "You know that whatever I say, Altera will violently disagree with."

And does it ever.

"It's hogwash!" retorts Bob Beachler, Altera's manager of strategic marketing. Warming to the argument, he further derides the Actel stance as "inaccurate, and [he's] misleading the market place. What John is trying to do is group all CPLDs together. The fact is, there are CPLDs that are good for doing different things."

Both East and Beachler, like the industry and customers, are well aware of the basic strengths each device architecture has going for it. By integrating a number of fast PALs, CPLDs can get higher system speeds for typical lower-gate-count designs. Furthermore, the PAL-like macrocells and well-defined interconnections make the CPLD speeds highly predictable.

As a result, these devices quickly became popular in such equipment as complex state machines where operating speed is of the essence. It is the more highly integrated FPGAs, however, that have hit it big in fast-growth datapath computing, where lots of registers are the key for such things as buffering, switching, multiplexing, or processing data. Another FPGA benefit, albeit one gained at the expense of predictability, is more design flexibility. This comes from their multiple routing paths, something made possible by the gate array structure. A low-current requirement also is an advantage, especially in contrast to CPLDs, which eat up the power with each increase in speed.

Until recently, these major differences have kept the two architectures on non-colliding courses. The question, therefore, is: what's changed to escalate things?

The answer is clear. The big growth in programmables is unfolding as the logic sockets in new designs need higher density and performance from devices. Neither camp can afford to let these go by architectural default, so the new programmable generations offer improvements that can go after many heretofore unlikely applications. The intensifying competition is bound to cause more fireworks, especially as the advanced programmables now appearing are increasingly multifunctional, incorporating features from the other camp.

CPLD leader Altera is a prime example of how a firm is covering more bases. Its FLEX 8000 CPLD, implemented in SRAM process and therefore sometimes mislabeled as an FPGA, is a high gate count family optimized for registered logic that aims squarely at datapath computing, FPGA's own turf. The brand-new MAX 9000 family, announced last month, has a fast-track 3-dimensional interconnect scheme that further improves the CPLD features. Also, since October, Altera has been digesting its acquisition of Intel's programmable business, which gives it a pure FPGA line for the first time.

Interestingly, CMOS FPGA leader Xilinx Inc. (San Jose, CA) doesn't devote much marketing attention to selling against CPLDs. Its major thrust instead continues to be taking away the low-end gate array market. Their introduction of the XC5000 family (with density up to 15 kgates and 3-layer metal technology) late in November further confirms this direction. Xilinx' new logic and routing architecture, VersaBlock Logic and Versa Ring, is intended to give designers more application choices than they have with present FPGAs. This capability expands the FPGA sphere. Notes Chuck Fox, Xilinx' vice president of product marketing, "Users want programmable flexibility, and the XC5000 gives it to them."

Planting a foot in both architectural camps is certainly solid strategy, and something that Cypress Semiconductor (Sunnyvale, CA) and Atmel Corp. (San Jose, CA) are quick to point out that they have been doing all along. Both have strong product lines on either side. Cypress doesn't address this issue with its programmable logic customers one way or the other at first meeting. "We recommend to designers that they don't specify [an architecture] in advance," says Norm Taffe, who manages product marketing for both FPGAs and CPLDs. "Just do the design, and we'll get the right device." But he can't resist the opportunity to throw a punch at one-product competitors: "The user should be wary of the company only offering one or the other."

Atmel's Joel Rosenberg, manager of programmable marketing, sees it in the same way. Noting that having choices available certainly builds credibility with customers. Atmel, with its PAL-type V-Series CPLDs and AT6000 FPGAs, has the entire range as does Cypress. Rosenberg is clearly an FPGA proponent, however, as he strongly believes that SRAM technology still has the edge in features, cost per gate, and power. An even bigger square-off between two device approaches is looming, in his opinion, as antifuse improvements allow these FPGAs to challenge SRAMs particularly on cost.

In Rosenberg's view, the marketing heat emanating from present selling disputes is interesting, but will have little lasting impact. "The issue [of one architecture versus the other] is one that is more important to vendors than to users," he says. What customers want (and since Rosenberg is on the road seeing them most of the time, his opinion is based on solid data), "is for vendors to solve their design problems. They don't really care how."

Larry Waller is contributing editor of ASIC & EDA, Technologies for System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  December 1994