Programmable Notes

Hooray or Ho-Hum? Do Altera's new FLEX 10K embedded arrays deserve a hooray or a ho-hum? It depends on who's talking about them... by Larry Waller

Even at the break-neck pace with which the programmable logic business churns out developments, some things stand out from the crowd. The new FLEX 10K family of embedded programmable logic devices from Altera (San Jose, CA) surely qualifies as one of them.

For openers, Altera has come up with the industry's first embedded programmable architecture. On this score alone, the FLEX 10K has to be considered a seminal programmable logic development, something too important for competitors to blithely discredit or ignore. Comments being made throughout the industry since Altera unveiled the new FLEX in March already confirm this.

The FLEX 10K is significant for its market positioning, which, in the company's words, "moves programmable logic further into the mainstream." The architecture's embedded array blocks support the design-in of numerous memory-dependent functions hitherto impractical in FPGAs and CPLDs (whose limited densities were not up to the heavy bit/gate overhead of implementing SRAMs, for instance). According to Altera, with the new architecture, the devices can now step up to challenge today's full-fledged gate arrays.

Altera's vice president of marketing, Erik Cleage, notes, "We can now execute memory and specialized logic functions with the same kind of efficiency and speed as embedded gate arrays."

This capability puts Altera's new family into one of the hottest segments of gate arrays, according to Dataquest market information. Embedded gate arrays are increasingly being used to reduce die area and increase speeds compared to standard arrays, besides offering on-chip memory to implement such complex functions as microcontrollers and microperipherals. At present, over 40 percent of gate array design starts use some form of the memory function, especially at gate densities above 50k. Because the industry's taste is notably geared to appreciate a blockbuster announcement, reaction to the Altera FLEX 10K is mostly favorable. The market consultant crowd in particular knows an important development when they see one.

"[This is] a very innovative architecture," observes Ronnie Rohleder of Pace Technologies (Scottsdale, AZ), "and an interesting way of making more comprehensive functions available." While the idea has been considered previously, Rohleder concludes that "Altera's family is a good way to do it," and competitors likely will have to go the same direction to keep up.

Will Strauss of Forward Concepts (Scottsdale, AZ) offers kudos because "Altera allows greater functionality on a die at a lower price." An industry watcher of nearly two decades' standing, Strauss believes that those who will benefit particularly are smaller OEMs who didn't have resources for full gate array development. "[FLEX 10K] will empower them to get out of board-level designs and into ASICs," he says.

Many veterans also recognize that introduction of the embedded arrays amounts to programmables taking another step along the same path blazed in the late '80s by gate arrays. Jim Panfil, director of marketing at LSI Logic (Milpitas, CA), is one. Says Panfil, "imitation is flattering. I suppose that's because it reinforces the direction we've taken." LSI has been a pioneer in multifunction ASIC devices since the '80s with its CoreWare family of standard cell products, which offer up to 1.5 million-gate densities.

Amidst all the upbeat commentary, Xilinx (San Jose, CA) is presenting a decidedly contrary view. This reaction comes as little surprise to observers, who expect sparks to fly whenever the two arch-rivals address an issue. They are squared-off presently in patent litigation while battling for design sockets with users in the marketplace, and vying for overall programmable logic leadership.

Anyone could have predicted Xilinx would have a confrontational position on the Altera move. It was Chuck Fox, director of product marketing, who enunciated it: "It is a big fallacy," he said, "that pre-partitioned functions [such as Altera's FLEX 10K] are more efficient than arrays." Fox bases Xilinx's view on limitations it sees in the new programmable architectural approach. As described by Fox, its reputed advantages are not surprisingly less than overwhelming.

Altera's FLEX 10K architecture provides multiple memory and specialized logic functions in embedded array blocks (EABs). These blocks are supplied on-chip along with the logic array blocks (LABs), which are larger versions of the LABs used in Altera's FLEX 8000 line of CPLDs. The EABs can be regarded as "a sea of programmable bits" as the company puts it, which can be configured to perform a number of memory and logic tasks.

By contrast, Xilinx with its XC4000 family of FPGAs already offers SRAM cells distributed throughout the array, which can be configured with software tools into special functions. Fox says it is similar to the way gate arrays use memory, "so we do it, too."

The issue thus becomes one of Altera's embedded programmable architecture versus Xilinx's distributed-memory approach. Fox points out a number of ways his scheme is better. A basic limitation is how the Altera family's density is figured, he points out. Because the rival company "is imputing gates from memory bits," the gate count of such devices as the 100-kgate EPF10K100 is grossly overstated and therefore very misleading, in Xilinx's opinion. "This is a disservice to the industry," he says. Furthermore, the new family retains what Fox calls the pin-out limitations of the FLEX 8000 architecture, which cannot easily be varied.

At Altera, such charges are dismissed as sour grapes. R&D on the new family has been underway there since early in the decade. "This is the way programmable has to go," notes Bob Beachler, who directs Altera's strategic planning. "We wanted to do state of the art ASICs, not muddle around with the sea-of-gates thing that has been around for years." He scoffs at the charge that the gate counts are fudged, and points out that initial specs present usable gates as a density range, against a specific RAM bit capacity. The EPF10K100, for example, with 100k typical gates, has a usable range of 69.5-170 kgates depending on configuration, with 26.624 RAM bits. It will be available in the fourth quarter, following the first FLEX 10K to hit the market, the 50-kgate EPF1050, in the third quarter.

As for the important interconnect feature, which is critical to place and route, Altera has enhanced its FLEX 8000 FastTrack scheme by some 50 percent. These rows and columns of on-chip wire that span the length of the die provide the routing resources to connect the EABs and LABs in the desired logic and memory configuration.

Altera has a lot of work to do in coming up with the comprehensive support needed to get the new family going later this year. LSI Logic's Panfil warns that the cell library and software are the big hurdles. His firm learned this lesson in its pioneer role. Altera is committed to providing an ambitious cell library of megafunctions that include 8086, Z80, and 6502 microprocessors and controllers, along with the memory, arithmetic, and DSP capabilities. These will be provided in the library of parametric modules (LPM) format for accessibility and flexibility of design, according to Beachler.

Altera has yet to announce detailed performance specs and a firm price list, but presentation materials promise 75 MHz system performance, and Beachler says the tabs on the top-line chips will be "less than $500 and dropping fast," and the lower tier should be about $25 apiece.

If industry chatter means anything, Altera's competitors already are convinced they have to have a comparable embedded entry, and soon. Pace Technologies' Rohleder sees this happening later this year. Beachler agrees, noting that this will underscore the significance of Altera's development. "This is the future direction of the industry. Others have to do something similar."

Larry Waller is a contributing editor at Integrated System Design.

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integrated system design  July 1995