Programmable Notes

10-K Density Wall Still Affects FPGA's Designers need better tools to handle the larger programmable devices. by Larry Waller

If anyone still doubts the absolutely critical role that good EDA tools play in supporting the soaring programmable market, they haven't been paying close attention.

Most recent demonstration (during 1995) of their value concerns questions surrounding the so-called FPGA 10 kgate "wall." As some astute observers describe it, this term is shorthand designation for what amounts to a barrier reef of complexity, hindering users in a smooth move up the density ladder from simple PLDs. Other equally qualified observers take issue with the wall concept, however. They note that any design problem associated with higher-density chips is simply a growing pain of fast-moving business. For one thing, customarily silicon developments industry-wide have outpaced the software necessary to support them.

As recounted by wall proponents, the EDA tool problem is the real one, and familiar to any designer grappling with the challenges posed by new, higher-density devices. Yesterday's software tools, tried and true with simpler parts, are falling short of getting higher levels of silicon performance. Furthermore, this has been the common experience of two quite different types of customers--those moving up the programmable-density ladder from PLDs, and the more sophisticated ASIC types looking into replacing masked gate arrays with FPGAs.

While few silicon vendors argue that EDA tool development for programmables is needed, it is not surprising that they also tag the other fellow as having the biggest dilemma. "We haven't seen the wall as the problem," notes Bob Beachler, strategic marketing manager at Altera Corp. (San Jose, CA). "Our customers are not telling us that."

But if one of the most-telling indicators that a problem generally exists is a proliferation of improvements that deal with it (without admitting a thing), then announcements in recent months heartily confirm that silicon vendors are wasting little time in correcting it.

As the FPGA industry leader, Xilinx Corp. (San Jose, CA) can be expected to be in the vanguard. "It is absolutely essential to bring enhancements to design," observes Kenn Perry, director of software marketing. A former employee of software independent NeoCad, acquired earlier this year by Xilinx , Perry, and other people from the EDA operation are playing key roles at the firm whose biggest growth strategy targets replacing 10 to 20 kgate arrays with FPGAs.

With its leading position, Xilinx has been closer to the 10k wall than others, according to industry chatter. Its XC4000 family, with entries such as the XC4025, has been on the market for more than a year, addressing the lower part of the gate array business.

FPGAs such as these with SRAM architecture possessing coarse-grain granularity, are most on the spot, sources say. The hangup is reportedly with the place-and-route backend tools that worked well at lower densities, though often augmented with lots of manual tuning. But the increased gate counts raise the complexity of efficiently routing logic on a FPGA device.

The problem is the timing-delay dilemma of most FPGA architectures, caused by the inherent unpredictability of logic paths laid out somewhat randomly. The need is for better software routing algorithms and improved synthesis techniques, according to most knowledgeable EDA officials. In the view of Steve Eichenlaub, marketing manager at Mentor Graphics (Wilsonville, OR), "Bigger parts need robust, more sophisticated algorithms." Fine-grain CPLDs and antifuse chips are also subject to some of the same constraints but to a much lesser degree, most sources say.

In Altera's view, the lag in tool development is more of a "design gap in which the amount of logic available in PLD is growing faster than the ability of the designer to fill it." What is called for is to improve productivity by using synthesis more effectively, says Beachler.

Xilinx accordingly is fast upgrading its software, most recently by bundling a number of improvements with NeoCad's Foundry FPGA design package. NeoCad's place-and-route tools are a key part of the upgrade since they work better than Xilinx's own proprietary software for this purpose. For high-density requirements, Xilinx's new XCATstep Advanced software provides support for the XC4000 line, with a synthesis option capability a key part of the new offering.

The Xilinx software is by no means the first to deal with high densities. AT&T Microelectronics' SCUBA (Synthesis Compiler for user programmable arrays) has been available for more than a year for its high-density ORCA series of FPGAs. Using high-level languages for design entry, it supports automated layout with logic synthesis and optimized built-in macrofunctions.

Another newly announced EDA tool with all the right things going for it is Actel Corp.'s Directing package. It features a much-improved timing-driven place-and-route algorithm that eliminates the need for manual intervention by designers. Actel is one of the few firms introducing new design software in advance of new devices, which is the right way to do it but seldom achieved by most companies. Actel's new 3200DX family of FPGAs debuts this summer.

Those tools intended to bring programmable software up to the advanced silicon levels are fascinating to watch, to be sure, because of their impact on the growth factors. A typical view is offered by Rita Glover, president and founder of EDA Today (Phoenix, AZ) who observes, "A lot of these tools coming out now are changing the scene."

But what is perhaps more intriguing is what these changes mean and how they fit into the bigger EDA picture.

One event assuming enhanced importance is Xilinx buyout of NeoCad, which at the time was largely dismissed as an opportunistic stroke by the programmable leader in removing an independent software asset from the reach of such competitors as AT&T and Motorola Semiconductor. "That's how I saw it at the time," remarks one programmable official, "but now I believe it is more than that."

Glover and Mentor Graphics' Eichenlaub both agree the acquisition also served as a triggering event, from which other developments flow. "It shows that silicon vendors really want to control their own back-end tools," she says. In the past few years, there has been much talk that these proprietary layout, place-and-route software design capabilities could become universal as the widely used DE packages of the gate array world. But this view was soundly derailed by the real programmable world where innovations arrive at breakneck speeds that outside EDA tool developments cannot match. "Now they realize that software and silicon developments must proceed in tandem," Glover says. Eichenlaub believes that for this reason silicon vendors will keep firm control over place-and-route tools.

But it is also becoming clearer that programmable firms will depend on the top-down design platforms supplied by EDA vendors. These will provide the vital front-end functions such as design entry, simulation, and synthesis. Examples abound of solid relationships between EDA houses and silicon suppliers as this trend picks up momentum, Eichenlaub notes.

All in all, some see the perception of a software wall as a healthy competitive development. For one thing, it evidently has somewhat slowed established programmable firms from claiming the higher-density business as a simple extension of their turf. Actel's Product Marketing Manager Tom Todd in fact foresees "a leveled playing field" that should aid companies such as his as higher-density chip sales soar. Some industry analysts go even further, predicting a pickup in new entries once again. Recent announcement of the new FPGA family from the Gatefield division of Zycad Corp. (Fremont, CA) is only the beginning, they say.

Larry Waller is a contributing editor to Integrated System Design

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  September 1995