IN THE NEWS

Business and technology news from the semiconductor and design tool industries.

High-Density Gate Arrays Debut

Two companies have introduced gate array products that overshadow previous industry announcements in gate density.

NEC Corp. (Mountain View, CA) announced the availability of a new gate array family of 20 base arrays with up to 2 million gates and 1,204 I/O pads. These design kits are now available for the new array family in their 0.35µm CMOS-9 technology. The array has two or three levels of metal for interconnections in a sea-of-gates architecture. The array supports system clock speeds of up to 155MHz. NEC will accept designs for the new array families starting in March 1995.

Also, IBM Microelectronics (Essex Junction, VT) announced the availability of a new gate array with up to 1.6 million gates available in their 0.5µm (0.36µm eff) CMOS 5S process. The array has five metals plus a local interconnect for macro cells, and can use up to 736 pins for I/O. Design kits, as well as a library of functions including processor and communications cores, RAM, ROM, registers and other functions, are available now. The libraries are optimized for 3.3V operation. IBM includes automatic test pattern generation with all of their ASICs.

Bryan Lewis, director of ASIC services at Dataquest (San Jose, CA) says that these announcements from industry technology leaders will be the first of many. In spite of the sizes of the new arrays, the user is cautioned to evaluate these products on actual utilized versus raw gate count. Dataquest projects that for 1996, only 10 percent of new production will use 0.35µm process technology; the balance will be in 0.5- to 0.6µm or larger. Lewis is projecting that of all new gate array designs in 1996, 21 percent will utilize more than 100 kgates, while 33 percent of all cell-based designs will use over 100 kgates.

These large arrays, with others to follow from other vendors, will put additional strains on the development tools and the whole design process. These very high performance, very high density arrays require much closer coordination of the design, layout, and test functions, since the final performance depends on the actual layout and the added structures needed for testing. This level of integration will also demand much greater detail in developing the timing and signal path constraints which will drive the layout and test pattern generators. These large arrays will also require more extensive libraries of higher order functions.

Bob Payne, chief technical officer and vice president of ASIC core technology at VLSI Technology (San Jose, CA) sees trends towards more structured solutions, using pre-designed blocks of RAM, datapath, and other cores. He also sees greater migration towards more cell-based designs and a move in the level of abstraction at the design level towards behavioral synthesis.

The vendors are helping to address some of the issues by providing their proprietary software for some of the back-end functions, or by performing the back-end functions themselves. "There will be many challenges ahead," Payne says. "The design methodologies will change to help to step up to the challenges."

From IBIS, an update

The IBIS Open Forum, a group made up of electronic design automation and semiconductor companies, announced on December 9, 1994, the acceptance of the I/O Buffer Information Specification (IBIS) revision 2.1 standard for integrity models. The refined standard adds support for ECL, dual-supply buffers, ground bounce due to shared power rails, differential I/O, termination components, controlled rise-time buffers, much more complete package descriptions, and reference waveforms.

They have also created a v2.1 of the "golden parser" that checks model syntax for conformance to the specification. It is currently being Beta tested; when completed, it will be made freely available in object code format.

IBIS is a consistent software parsable format that semiconductor vendors can use to specify the analog characteristics of input and output buffers. This information is readily transformed into accurate models by end users and simulation tool vendors. The resulting behavioral models enable users to perform high-speed, accurate signal-integrity simulations of their digital system interconnects.

For more information about the IBIS Open Forum, send an e-mail request to IBIS at ibis-info@vhdl.org. All of the documents and publicly available models are currently accessible via the public repository of VHDL International's Internet-based machine (vhdl.org, 198.31.14.3, http://vhdl.org/). WWW, Gopher, FTP and Telnet "Anonymous," and "guest" dial-in access, (415) 335-0110, are all available.

Design SuperCon debuts in Santa Clara

Three industry magazines ( EDN, EE Times, and Integrated System Design ) and Hewlett-Packard are pooling their resources to put on Design SuperCon '95. The conference is actually three conferences in one, focusing on high-performance system design ( EDN 's entry), digital communications design ( EE Times ), and on-chip system design ( Integrated System Design ). Each sub-conference will feature between 36 and 51 papers for practical design lectures, tutorials, and panels.

The On-Chip System Design Conference (OCSD) features several sessions: system architecture, design methodology, chip realization, and OCSD management. In addition, there will be panel sessions interspersed throughout the conference providing a dialog format for current topics and issues. Speakers in the different sessions will share their experiences and expertise in all areas of on-chip system design.

Design SuperCon is focused on practical design issues, and this will be reflected in the presentations and on the demonstration floor. Priority has been given to vendors who could demonstrate their tools or technologies applied to everyday design problems. Many of these demonstrations are tied to issues and problems addressed in the papers.

The conference is being held Feb. 28-March 2, at the Santa Clara Mariott in Santa Clara, CA On-site registration is $115 for one day, $175 for two, and $235 for three days. For more information, call 1-800-722-7842.

EDIF updates PCB standard

The Electronic Design Interchange Format (EDIF) Division of the Electronic Industries Association (EIA) has announced the release of the EDIF printed circuit board standard, EDIF v.3 5 0. With this release enacted, the process of transporting PCB layouts between CAD systems has been simplified.

EDIF PCB enhances the existing EDIF release beyond connectivity and schematics to encompass support for PCB design, manufacture, and assembly. Included is support for parts, packages, bare boards, and assembled boards. It consists of a formal model of the information it uses to represent a PCB/PCA, and a reference manual describing the syntax and examples.

Key features include the ability to handle simple layout features, complex sub-layouts, padstack usages, physical nets, sub/nets, and layout text.

Copies of EDIF v3 5 0 are available in electronic format for $100 and may be obtained from Ms. Patti Rusher, at EIA. Phone: (703) 907-7545, fax: (703) 907-7501.

AMD, Intel reach agreement

Advanced Micro Devices (AMD, Sunnyvale, CA) and Intel Corp. (Folsom, CA) have announced that they have reached an agreement to settle all outstanding legal disputes between them. The major points of the agreement are:

AMD will have a perpetual license to the microcode in the Intel 386 and Intel 486 microprocessors, but AMD agrees that it has no right to copy any other Intel microcode (including the Pentium and 486 ICE).

The companies will negotiate a new patent cross-license agreement to become effective Jan. 1, 1996.

Intel will receive $58 million as a settlement for past damages in the 486 ICE case. As ordered in the 1992 arbitration, Intel will pay AMD approximately $18 million (which includes interest) awarded by the arbitrator for breach of contract, and will not contest rights granted AMD in the arbitration award.

Intel and AMD will drop all cases including appeals currently in the courts. They also agreed not to initiate any legal action against one another for any activity occurring prior to Jan. 6, 1995.

AMD will have the right to use foundries for AM486 products containing Intel microcode for up to 20 percent of its 486 production.

In a joint statement, Richard Previte, president and chief operating officer of AMD, and Craig Barrett, executive vice president and chief operating officer of Intel, said they were pleased, and that the agreement "is clearly in the best interests of our customers, our stockholders, and the PC marketplace." Previte and Barrett were the lead negotiators of the agreement.

Viewlogic's financial results below expectation

Viewlogic Systems (Marlboro, MA) announced revenues and earnings for the fourth quarter (ended Dec. 31, 1994) would be significantly less than had been anticipated. Based upon information available in early January, the company estimated fourth quarter revenues would actually show only a nominal increase over the corresponding period of 1993.

The results of the financial announcement had a serious effect. Viewlogic stock, which had been selling for $24 in early November, reached an all-time low of $7 7/8. (The record high was $30, set back in February, 1994.) As of the end of January, their stock was back in the $9-$10 range.

In addition to the stock market difficulties, the actual financial figures released in late January raised some eyebrows. Fourth-quarter earnings in 1993 were $5.5 million, but only $95,000 in 1994; total 1993 earnings were $13.7 million, but for 1994, the company recorded a $6.3 million loss.

Contributing to the loss were such non-recurring items as the $15.4 million acquisition of Sunrise Test Systems and the $3.1 million acquisition of Chronologic Simulation. Averaged out, the company was actually making money, but at a slow rate.

Viewlogic attributes the fourth-quarter revenue shortfall to several factors, including a "weakness in demand" for its schematic entry design products. Certain products, anticipated to be delivered in the fourth-quarter, had to be rescheduled for 1995, also contributing to the problem.

Rita Glover, president and principal analyst at EDA Today, considers the flap "an aberration, and they're getting a bum rap from Wall Street." Since 70 percent of the stock is held by institutional investors, it has a serious effect if they pull out. Glover believes that Viewlogic is actually in great shape, and their stock is probably a good buy. "The market is just starting to change," she says, "and we're starting to see it right here."

Cadence acquires Parsec

Cadence Design Systems (San Jose, CA) has acquired Parsec (Los Altos, CA). Parsec's principal product is Pearl, a fast, high-capacity static timing analyzer for ICs. The acquisition is a boost for Cadence, who considers the move another piece of their deep submicron strategy. Pearl is driven by the deep submicron imperative for advanced timing solutions, and supports full chip timing analysis for complex multi-million transistor ICs. It is said to run at least 10 times faster than competitive tools.

James Cherry, president of Parsec and the developer of Pearl, is now an management-level employee of Cadence.

The specific terms of the acquisition were not released.

NewsBytes

ANACAD EES (Milpitas, CA) has signed an OEM agreement with Viewlogic Systems (Marlboro, MA) to enable ANACAD to customize and resell analog and mixed-signal solutions integrating its mixed-signal simulation tools with Viewlogic's Powerview environment.

Cadence Design Systems (San Jose, CA), SGS-Thomson (San Jose, CA) and Philips Semiconductors (Albuquerque, NM) have agreed to cooperate in producing a comprehensive System for Library Development (SLD). The SLD will produce a library solution that allows silicon processes, libraries, and design environments to be developed concurrently, reducing overall IC time-to-design-start by two to three times.

Cadence has signed a multi-million dollar, three-year agreement with Western Digital (Irvine, CA) to become their dominant EDA partner, defining and creating a new product development environment for Western Digital's IC products.

Scientific Atlanta (Norcross, GA) has placed an order with Intergraph Electronics (Huntsville, Ala.) for VeriBest EDA design tools and several other design software items, totaling $2.5 million. Sulzer Electronics AG (Winterthur, Switzerland) also placed an order valued at $400,000 with Intergraph for VeriBest and other design tools.

Altera Corp. (San Jose, CA) is reducing prices up to 57 percent on high-speed members of it MAX 7000 EPLD family.

PADS Software (Marlborough, MA) and Viewlogic will market specially configured and priced packages of their EDA software in the People's Republic of China.

Oki Semiconductor (Sunnyvale, CA) has received ISO 9002 certification for excellence in quality at its U.S. plant in Tualatin, Oregon.

ICCAD '95 (International Conference on Computer-Aided Design) will be held in San Jose, CA, on November 5-9. The organizers are making a call for papers. For information on submitting a paper, e-mail to: icupubpap@dac.com. For information on the conference itself, call (303) 530-4562.

NEC Electronics (Mountain View, CA) has announced that VSS Expert, the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys (Mountain View, CA) VHDL system simulator, has been certified as a sign-off simulator for three NEC gate array technologies. The "golden" simulator will support NEC's 0.5µm CMOS-8L, 0.6µm CMOS-8, and 1.0µm CMOS-6 gate array families.

Cirrus Logic Inc. (Fremont, CA) has licensed an innovative interface technology from Rambus Inc. (Mountain View, CA). The technology uses the Rambus DRAM architecture, and supports 500Mbyte/sec data transfer rates from a single device.

The Sixth International Conference on Signal Processing Applications & Technology ( ICSPAT '95 ) is issuing a call for papers. The conference is to be held in Boston, MA on October 24-26. E-mail to icspat@dspnet.com. For more information on ICSPAT, contact (617) 891-6000.

Data I/O (Redmond, WA) and Altera are co-developing the algorithms for devices to be programmed on Data I/O systems. This is intended to shorten the time-to-market for programmable integrated circuits by shortening the process of developing and refining device algorithms.

Accel Technologies (San Diego, CA) and Altium (San Jose, CA) announced the pending sale of Altium's P-CAD business to Accel.

Summit Design (Beaverton, OR) has signed an exclusive agreement with Anam Semiconductor and Technology (Seoul, South Korea) to allow Anam to market its products in South Korea.

Xilinx (San Jose, CA) will be the first programmable logic supplier supported by high-level design automation (HLDA) supplier Escalade (Sunnyvale, CA). Escalade will offer an HLDA environment, the DesignBook (see Tools and Technology), to support the Xilinx XC4000 family of FPGAs.

Movers and Shakers

Aurelio E. Fernandez has joined IC Works (San Jose, CA) as vice president of worldwide sales.

High Level Design Systems (Santa Clara, CA) has promoted Bob Wiederhold to the newly-created position of executive vice president and chief operating officer.

Silicon Valley Research (Mountain View, CA) has appointed Dr. Han Young Koh director of technology.

ANACAD EES (Milpitas, CA) has named John Zuhosky to the position of southwestern U.S. regional sales manager in the newly-opened Texas office.

The new sales development manager of CVD Silicon Carbide at Morton International (Woburn, MA) is Gail L. Dewey .

Chrysalis Symbolic Design (Andover, MA) has named Leonard I. Major vice president of finance & administration and chief financial officer. R. Kent Blackett has joined Chrysalis as vice president of engineering.

David Cheung has been named senior vice president of engineering for Credence Systems (Fremont, CA)

Micro Component Technology (St. Paul, MN) has hired L. David Sikes as president and chief executive officer.

Dr. Richard Newton of the University of California at Berkeley has joined the Board of Directors of Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys .

ASIC International (AI, Knoxville, TN) has hired Daniel J. Lincoln as director of technical field service. Henri A. Jarrat has been named to the board of directors of Paradigm Technology (San Jose CA).

Cooper and Chyan Technology (CCT, Cupertino, CA) has appointed Jack Harding president and chief executive officer.

MoneyBits

Advanced Micro Devices (Sunnyvale, CA) reported record year-end sales for 1994 of $2.1 billion, a 30 percent increase over 1993. Operating income was $508.7 million, up 67 percent from the previous year.

Paradigm Technology (San Jose, CA) announced a new record sales level of $10 million for the quarter ending 1994.

IKOS Systems (Cupertino, CA) announced its fifth consecutive quarter of increased revenue and earnings. The first quarter earnings (ended Dec. 31, 1994) were $6.1, compared to $4.8 for the same quarter last year.

Quickturn Design Systems (Mountain View, CA) announced 1994 year-end revenue of $65.5 million, a 19 percent increase over 1993 year-end revenue of $54.9 million. Net income was $4.6 million.

High Level Design Systems (Santa Clara, CA) reported record revenues of $1.2 million for the third quarter (ended Sept. 30 1994), representing a 32 percent increase from the same quarter in 1993.

Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys (Mountain View, CA) has announced a revenue increase of 31 percent, and a net income rise of 43 percent in their first fiscal quarter (ended Dec. 31, 1994) over the same period the previous year. Revenue is reported at $58 million, and net income is $7.5 million. For fiscal 1994, they reported net income of $15.8 billion, and a revenue of $196 million.

Cadence Design Systems (San Jose, CA) reported revenue of $121.7 million for the fourth quarter ended Dec. 31, and a net income of $20.9 million. Revenues were up 15 percent from the same quarter in 1993. For the year ended Dec. 31, revenue was 429.1 million, up 16 percent from 1993's total of $106.1 million.

Altera Corp. (San Jose, CA) reports fourth quarter sales of $59.2 million (up 44 percent from the same period in 1993; up 21 percent from the previous quarter). Total 1994 sales were $198.8 million, a 42 percent increase over 1993.

Integrated Silicon Systems Inc. (ISS, Research Triangle Park, NC) had fourth quarter (ended Dec. 31) revenue of $4.1 million, up 38 percent from the same time in 1993, and a net income of $1 million, an increase of 31 percent.

integrated system design  March 1995