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TOOLS AND TECHNOLOGIESProducts and services for system designTool supplier expands offering CORE/Analyze is the newest addition to Exemplar's line of design, synthesis, simulation, and analysis tools for CPLD, FPGA, and ASIC designers. CORE/Analyze adds static timing analysis, schematic generation, and backannotation to the company's CORE/V-System high-level design environment. It will support the Xilinx 3000 and 4000 series of FPGAs and the Xilinx 7000 series of EPLDs. The product's release coincides with the release of CORE Version 2.2, which offers additional ModGen support for Verilog and VHDL constructs, additional Verilog and VHDL operators, and Boolean mapping for Actel FPGAs. CORE Family pricing starts at $8,000 for PCs and $25,000 for workstations. Shipping for CORE/Analyze and CORE Release 2.2 begins in February. Exemplar Logic Inc., Berkeley, CA. Contact Kieran Patton: (510) 849-0937
Single-step process for ASIC placement Silicon Synthesis merges placement and logic optimization algorithms into a single-step process for logic designers. It is intended to effectively eliminate design iterations typically incurred using methodologies based on estimation for deep submicron design. Cadence's Silicon Synthesis technology is based on (and an enhancement of) their Q-Place and Placement-Based Synthesis, merging them into a single process aimed at front-end designers. Cadence is targeting delivery to start in the first half of 1995. Cadence Design Systems Inc., San Jose, CA Contact Mike Sottak: (408) 428-5036 ABEL to work with Windows ABEL, a popular behavioral entry design software for CPLDs and PLDs, is now available for those operating in a Windows-based PC environment. ABEL 6.0 for Windows arrived in time for the tenth anniversary of the original DOS release. It continues to support virtually every PLD on the market, and can design devices up to 10 kgates. The software is device independent, allowing the design to be written independently of any device and mapped to many different architectures automatically. New features include ABEL Project Navigator, which presents a checklist of processing steps customized for the specific device targeted, and full hierarchical support. ABEL 6.0 is available now for $2,295. Existing ABEL-DOS customers with current maintenance contracts are entitled to a free upgrade. DATA I/O, Redmond, WA Contact: 1-800-332-8246 Practical, low-cost IC design tool MyCAD is an IC design and layout tool for engineers who want low-cost, practical desktop EDA. It is modularized to allow the user to select what he needs. Modules include MyLogicStation schematic capture, which supports multi-window and multi-edit functions, unlimited hierarchical design, and output to AIM-SPICE, and MyChipStation, a custom layout editor with unlimited hierarchical design, a customizable design environment, and polygon-based any angle/shape geometry. Other products available include a self-training kit. All products are available for Windows 3.1, WindowsNT, and SPARC, but MyVHDL, MySynOpt, and the VASE 8010 kit are available on SPARC only. Pricing starts at $595 per module for the PC platform, and $1,195 for the SPARC platform. Agape Design Automation Co., Sunnyvale, CA Contact Frank Johnson: (408) 745-6785 Silicon building block for serial storage architecture The VCF94200 is a silicon building-block implementation of a dual-ported serial storage architecture (SSA) function. This functional system block (FSB) cell may be embedded into either an ASIC chip or into an application-specific standard product, resulting in storage interconnect subsystems with reduced part count, lower power dissipation, and lower cost. Applications could include controllers for redundant arrays of independent disks, I/O controllers for connecting storage devices to mainframe computers, workstations, and even PCs. Serial storage architecture simplifies cabling and enables data to be transferred faster than through parallel interfaces. It also offers fault tolerance and hot plugging. The VCF94200 SSA FSB cell is fully compliant with serial storage architecture SSA-PH specification, with each port providing 20 Mbytes per second full duplex operation. Design files for the VCF94200 SSA FSB are currently available. Designs of prototype chips incorporating the VCF 94200 may be started now, with production scheduled for the first quarter of 1995. VLSI Technology Inc. San Jose, CA Contact Tom Norton: (408) 434-7668 QuickLogic FPGA tool ACTIVE-QLOGIC is a Windows 3.1based FPGA development system for QuickLogic devices. It is a complete front-end, comprised of a schematic editor and pre- and post-layout simulators. The accompanying Design Manager integrates all QuickLogic related tools, and all software setups are performed from one central point within the Design Manager. With all project resources linked together in a single data base, design integrity is improved, and the entire design process is controlled from a single flow chart with active buttons. Design verification takes place while the design is drawn, enabling the designer to instantly correct errors as they occur. ACTIVE-QLOGIC is priced at $1,995. This price includes the Design Manager, schematic capture, on-line background logic simulator, and the entire QuickLogic cell library. ALDEC Automated Logic Design Company Inc. Newbury Park, CA Contact 1-800-487-8743
FLASH370 family grows Cypress Semiconductor's FLASH370 family of CPLDs has new members. The new CY7C372 and CYC373 are 64-macrocell versions of the FLASH370, with maximum propagation delays of 10 ns. These CPLDs are manufactured with 0.65µm CMOS Flash technology, thereby offering electrical erasability and reprogrammability for simplifying product inventory and reducing costs. The CY7C372 has 32 I/O pins and is offered in 44-pin PLCC and CLCC packages. the CY7C373 is optimized for high I/O applications, offering 64 I/O-pins in 84-pin PLCC and CLCC packages, as well as 100-pin TQFP packages. Both the CY7C372 and CYC373 are available now and supported by Cypress' Warp2 and Warp3 design tools. The CY7C372 is priced from $9.85 in 1,000-piece lots, and the CYC373 starts at $12.60. Cypress Semiconductor, San Jose, CA Contact John Hamburger: (408) 943-2902 A virtual circuit design lab for analog/mixed signal simulation ICAP/4 is billed as a complete circuit design and analysis package featuring schematic entry, analog/mixed signal circuit simulation, extensive device libraries, and powerful data processing, all in one interactive environment. Any kind of system that can be represented by algebraic or differential equations can be simulated, and digital and analog devices can be mixed. In addition, models can be system oriented or described at the device level. Other featured abilities include waveform cross probing, real-time waveform display, interactive measurements, and interactive parameter sweeping. The Interactive Command Language is a scripting language that allows the setting of "simulation breakpoints" that among other functions can stop a simulation when circuit performance has met a user-defined condition. A free demo disc is available. SMART Solutions, Milpitas, CA Contact Mike Saia: (408) 263-7010 To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com. [ Articles from Integrated System Design Magazine ] [ ICs and uPs ] [ Custom ICs and Programmable Logic ] [ Vendor Guide ] [ Design and Development Tools ] [ Home ] For more information about isdmag.com e-mail cam@isdmag.com For advertising information e-mail amstjohn@mfi.com Comments on our editorial are welcome. Copyright © 1996 - Integrated System Design Magazine
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