TOOLS AND TECHNOLOGIES

Products and services for system design

PCI-compliant EPLDs The XC73144 high-density erasable programmable logic device (EPLD) has a propagation delay of 7.5ns. The speed is 100 percent compliant with peripheral component interconnect (PCI) local bus specification. As with the rest of the XC7300 family, the XC73144 has a 100 percent populated switch matrix (universal interconnect matrix, or UIM), which allows the designer access to 100 percent of the chip's logic resources. The XC73144 is available in a 160-pin PQFP or a 225-pin BGA. Both packages accommodate either logic or I/O-intensive designs. Output drive is specified at 24mA, with an I/O interface for either 3.3V or 5V. It is supported by Xilinx EPLD Translator development software. Available speed grades are 7.5-, 10-, 12-, and 15ns. The 160-pin plastic quad flat pack versions are $59.90 each in quantities of 100 or more, and will be available in production quantity in March. Xilinx , San Jose, CA Contact Vallee Ghosheh: (408) 879-5085.

UNI device for ATM hubs and switches The VP67100 is a quad user network interface (UNI) device for manufacturers of asynchronous transfer mode (ATM) hubs and switches, SONET/SDH-based ATM switching system interfaces, and internetworking ridges and routers. It offers a 4x reduction in circuit board complexity. A transmission conversion sublayer function supports fixed (transmit) and fixed/floating (receive) frames. The cell delineation function implements cell rate decoupling, cell delineation HEC generation/verification, and unassigned cell generation at the ATM interface, according to CCITT specifications. The ATM-layer interface is through the UTOPIA standard, offering a 16-bit data bus operating at 50MHz. The VP67100 is produced using 5V 0.6µm CMOS technology, and is available in 250-pin plastic quad flat packs. Each costs $75 in 10,000-unit quantities. VLSI Technology Inc., San Jose, CA Contact Ramandeep Singh: (408) 434-7891.

New CMOS technology raises gate count, increases SRAM density CMOS 5S builds on IBM's CMOS 5L process technology by shortening the channel length for faster performance and adding a local interconnect wiring level for denser SRAM capability. The maximum usable gate count is 1.6 million gates, with a 0.18ns two-way NAND gate delay. This 0.55µm ASIC technology features a 0.36µm L-effective. CMOS 5S uses up to five metal wiring layers to achieve this gate-count level. The process also enables high I/O counts. CMOS 5S ASICS can easily be mapped from existing CMOS 5L designs and to future 0.25µm technologies. NRE charges for CMOS 5S vary depending on the complexity of the design and the quantity of the parts being manufactured. IBM Microelectronics, Fishkill, NY Contact 1-800-426-0181, ext. 321.

New synthesis family supports VHDL, Verilog-HDL ASIC, FPGA, and IC designers have a new plug-and-play tool in the AutoLogic II synthesis family, which offers support for both Verilog-HDL and VHDL. Newly incorporated technologies include Verilog-HDL and VHDL synthesis, Advanced Silicon Timing Package for deep submicron silicon, and Layout Sensitive Synthesis for links to Mentor Graphic's ASICPlan floorplanner. There are three family members: AutoLogic HDL (language synthesis), AutoLogic Optimizer (the core of the AutoLogic II tool suite), and AutoLogic BLOCKS (design creation and synthesization). Prices start at $48,000, although existing AutoLogic users under maintenance will get upgrades at no additional cost. Mentor Graphics , Wilsonville, OR, Contact Martin Lampard: (503) 685-1255.

Low-cost option for gate arrays The XC5000 family was designed as a low-cost field programmable gate array (FPGA) option aimed at capturing the low-end gate array market from manufacturers moving toward the higher volume, higher density applications. The SRAM architecture combines triple-layer metal with 0.6µm CMOS process technology, a new VersaBlock logic module, and VersaRing I/O interface. The die size is said to be 26 to 49 percent smaller than competing FPGA devices at this density. Design, simulation, and programming tools are provided under the Xilinx XACT software development system, while the Xilinx Alliance Program supports more than 50 third-party software vendors. XACT supports Unix workstations and PC environments. The XC5000 family includes the 6 kgate XC5206; the XC5215, a 10 kgate FPGA; and the XC5215, with 15 kgates. The 10K model is scheduled for high-volume production in the first quarter of this year. In volume, it is priced at $39. Xilinx , San Jose, CA Contact Vallee Ghosheh: (408) 879-5085.

TBGAs offer chip-mounting alternative High pin-count silicon chips (up to 672 pins) can now be accommodated with VLSI's new tape ball grid array (TBGA). Designers can create TBGA-packaged chips of more than 500 kgates and clock frequencies beyond 150MHz in 0.5- or 0.6µm CMOS technology. TBGAs offer twice as many connections per unit area of printed circuit board as compared to quad flat packs (QFPs), and cost less per pin than plastic pin grid arrays (PPGAs). While PGAs can only be through-hole mounted, TBGAs are surface-mountable. TBGA samples and prototypes are available, with full production scheduled for the first quarter of this year. VLSI Technology Inc., San Jose, CA Contact Eddy Perez (408) 434-7918.

Low-cost analog FPGA Electrically programmable analog circuits (EPACs) are the flexible analog equivalent to digital FPGAs. They are designed to minimize risk compared to other analog solutions, and provide designers with an alternative to printed-circuit boards, ICs, and analog arrays. EPACs are based on mixed-signal 1.2µm EECMOS process technology, with EEPROM. For low-volume production (up to 10,000 units), it is an appropriate solution; for higher volumes, IMP offers conversion of EPACs to mask programmable analog circuits (MPACs). Analog Magic software (running on a Windows-based PC) allows the designer to configure and program the functionality, interconnect, and performance of the EPAC devices. A starter kit, consisting of two sample IMP50E10 EPACs, Analog Magic, and a programming board is $299, while the full development kit (with two application boards, two IMP50E10s, Analog Magic, full documentation, and full evaluation system), is $1,169. Additional EPACs are available for $25 each in 100-unit quantities. MPAC conversion is quoted on an individual basis. IMP Inc., San Jose, CA Contact Hans Klein: 1-800-GET-EPAC (438-3722).

VLSI/Comatlas produce two new devices A forward error correction device and a demodulation device, jointly developed by VLSI Technology and Comatlas (Rennes, France), are on the market. The VY875453 forward correction device incorporates two error correction codes while requiring no external interleaving RAM. The first code is a Reed-Solomon outer shell for correcting byte errors, and the second is a Viterbi decoder inner shell for correcting bit errors in the incoming digital signal. It is available as a standard device or as a functional system block element. The device is packaged in a 68-pin PLCC, and is available for $28.25 in 10,000-unit quantities. The VY874123 is a single-rate coherent digital demodulator for BPSK and QPSK modulated signals. It can operate up to 60MHz, and with modulation rates to 30 MBauds. It is available for $17.65 in 10,000-piece quantities. VLSI Technology Inc., San Jose, CA, Contact Ed Begun: (408) 434-7912.

Reconfigurable DSP functions available Atmel has introduced a new class of applications software for developing in-system reconfigurable adaptive digital signal processing (DSP) hardware. High-speed DSP functions can exploit register-rich, dynamically reconfigurable FPGAs. The new DSP software facilitates quick and easy implementation of compute-intensive DSP functions, including multipliers, adders, accumulators, and more than 20 others. Users can specify the parameters of individual DSP functions including data width, pipelining, and other function-specific options. DSP function generators are included with Atmel's ATDS 2100 V.210b, and are provided to registered users at no charge. The software sells for $995. Atmel, San Jose, CA Contact Joel Rosenberg: (408) 436-4243.

Semicustom function blocks and libraries for PCI and mobile computing Semicustom Systems Interface Products are a new line of semicustom function blocks and libraries targeting PCI-bus and mobile designs. The new line employs the S-MOS SLA20000 family of semicustom products, the SLA30000 library (0.6µm), and several embedded semicustom products specifically designed for PCI and mobile computing systems. The first of these products includes a new PCMCIA Interface function block (SAM365). The PCMCIA I/O structure supports live insertions without damage or disruption to the host system. Other function blocks to be added soon are a SCSI 2.0 and fax/modem. The product family is supported by S-MOS' "universal design signoff support" where customers can sign off on the design in their native simulations environment. Current signoff support is available for Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys , Cadence, Viewlogic , and Mentor . NRE charges for libraries and function blocks, engineering and CAD support and prototypes begin at $20,000 and are dependent on design requirements. S-MOS Systems, San Jose, CA Contact Tony Truong: 1-800-228-3964.

integrated system design February 1995

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