TOOLS AND TECHNOLOGIES

Products and services for system design

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Front-end design tools The Source Design Tools Family, a new family of source-level tools for Verilog and VHDL design, are considered a major shift in hardware design. The shift is said to be analogous to the one that occurred in software design in the 1980s when the advent of source-level analysis and debugging tools eliminated the need to work at the assembler level. The suite consists of DesignSource (for source capture) and HDL Advisor (for source analysis). With DesignSource, designers can enter and edit designs using two graphical editors that directly reflect Verilog and VHDL structure. HDL Advisor, with two real-time analysis engines, is the first source-level performance analysis tool for high-level design. The suite is intended to allow designers to specify a design, check its performance, and track down any problems, all at the source level. The Source Design Tools Family (with both DesignSource and HDL Advisor) is $34,000. HDL Advisor alone is $24,000, and should be available in April. Design Source, at $17,000, should be available after July. Synopsys Inc., Mountain View, CA Contact Paula Jones: (415) 694-4112.

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Back-end design tools Designers working on deep submicron designs who need a parasitic extraction and delay calculation system for pre- and post-layout delay prediction can call on Fasnet RC Extractor and Fasnet Delay Calculator to help them. The two products work with High Level's design planning product line (Logic DP and Physical DP). Fasnet RC Extractor reportedly can extract distributed interconnect capacitance and resistance at speeds two to 10 times faster than other tools. A connectivity-based extraction technique allows distributed RC networks to be used directly by the Fasnet Delay Calculator. The latter considers both the effect of resistive shielding on gate delay and RC interconnect delay. Fasnet is available on Sun and Hewlett-Packard workstations. Fasnet RC Extractor and Fasnet Delay Calculator are sold as a bundle starting at $20,000 for a fixed node license, or $26,000 for a floating license. High Level Design Systems, Santa Clara, CA Contact Rochelle Perry: (408) 748-3456.

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FPGA family Actel's ACT 3 has a few new members in the family. Devices in the series with the suffix "-3" affixed to their listing are new. The family of fast, high-capacity field programmable gate arrays (FPGAs) offers 1,500 to 10k gates, and supports networking and graphics applications up to 150MHz, and DRAM and DMA controllers up to 75MHz. With clock rates up to 250MHz, the new "-3" suffixed members are twice as fast as the standard ACT 3 devices. The 2,500-gate A1425A-3 and 6,000-gate A1460A-3 devices are available starting at $56 in high-volume quantities. The A1415A-3, A1440A-3, and A14100A-3 will be available by July. Actel Corp. , Sunnyvale, CA Contact Bruce Weyer: (408) 739-1010.

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Peripheral chips Tired of getting headaches from the jaggies on your fax or printer output? The D9001LF from Destiny Technology could take care of much of the problem. Using their patented Edge Enhancement Technology, the new ASIC boosts resolution of unenhanced printed images several times and then divides the pixels into several "subdots." Programmable modulation registers in the D9001LF allow printer and fax manufacturers to customize it to work seamlessly with different print engines (LED and laser) at up to 600 dpi resolution. The chip can function within GDI, QuickDraw, PostScript Level II, and other printer languages. It even has a feature called TonrSavR that is intended to extend the life of the toner by allowing degrees of darkness. Destiny has also released another new ASIC, the D8805, intended to provide multifunction peripheral and laser printer designers with an inexpensive solution. It interfaces directly to the Motorola 68000 processor, and supports both Macintosh and PC platforms, providing built-in decompression for host-based printing. The D8805, a "three-in-one-chip, replaces three previous ASICs (the D6002, D8803, and D8804), the functionality of which it combines. Both the D9001LF and D8805 are available. Pricing is dependent on quantity. Destiny Technology Corp., Santa Clara, CA Contact: (408) 562-1000.

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High-level design tool High-level design automation (HLDA) is complex, requiring advanced levels of skill in HDL languages and a deep understanding of the technologies involved. DesignBook, intended to make working in HLDA simpler, is based on the concept of an engineer's notebook. It presents the designer with an integrated set of design capture and design management tools encompassing design intent capture, including functionality, implementation constraints, simulation stimulus, and library elements. It generates a complete design (including functionally correct HDL, simulation test vectors, and synthesis scripts), and so differs from tools that only generate HDL code from graphical paradigms. DesignBook supports all implementation technologies capable of using HLDA techniques, from FPGAs, CPLDs, and ASICs, to structured custom devices. Its graphically oriented editors include StateMachine Designer for control logic, Block Designer for block diagrams for data path, Equation Designer for Boolean equations, and VHDL Designer for VHDL entry. A selection of command and control modules (called "Commanders") to popular HDL simulators and synthesis tools is provided. Exemplar Logic and Model Technology 's V-System VHDL Simulator are available now; Verilog HDL and Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Commanders are planned for release in June. DesignBook is available on a Windows platform now for $14,500. The Unix software version should be out by July, and is priced at $25,000. Escalade, Sunnyvale, CA Contact Barry Mainz: (408) 481-1346.

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CPLDs AMD has a new range of CPLDs targeted at a broad range of applications like random logic, high-speed control functions, synchronous and asynchronous logic, and gate array replacement functions and control. Direct market applications include workstations, RISC microprocessor motherboards, and networking. The new offering includes a fast 128 macrocell CPLD, the MACH231-7. This chip features a fixed 7.5ns pin-to-pin speed and improved routing. The MACH231 comes in an 84-pin PLCC package. The MACH111 features twice the routing resources of the MACH110, and offers a fixed 7.5ns speed, 32 power-down macrocells, 32 I/Os, and 38 bus-friendly inputs. It comes in a 44-pin PLCC package. A 44-pin TQFP version of the MACH111 will be available by July. The MACH131 also features a fixed 7.5ns speed, and power-down macrocells that reduce power consumption by 50 percent over the MACH130. The MACH131 has 64 I/Os, and six dedicated inputs are bus-friendly. It is available in an 84-pin PLCC package. The devices are all supported by AMD's MACHXL design tool, and several OEM products. Advanced Micro Devices Inc., Sunnyvale, CA Contact: 1-800-222-9323.

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Xilinx - Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Interface update A new release of Xilinx - Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Interface and Libraries (XSI) for the Xilinx XC3000 and XC4000 families of FPGAs, and XC7000 family of EPLDS means enhancements for speeding the design process. XSI version 3.2 offers a complete and optimized solution from design concept through verification through new simulation models. It contains several improvements over the previous release, including new synthesis libraries offering timing estimates that match post-layout results within ±10 percent. Another improvement is to the design flow, allowing automatic I/O insertion and seamless integration with XACT 5.x. The simulation models provide full timing and gate-level simulation after layout, using the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys VHDL System Simulator (VSS). The gate-level accelerator in VSS is said to reduce simulation time up to 75 percent. XSI v.3.2 is supported by several platforms, including Sun-4, HP Series 700, and IBM RS/6000. It is shipping free to current XSI users on maintenance, and is available for purchase at $3,995 alone, or $9,995 when purchased with the complete XACT 5.0 software development system. Xilinx Inc. , San Jose, CA Contact Vallee Hubbard: (408) 879-5085.

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Voice recognition chip True voice recognition in personal computers, cellular phones, automotive electronics and other portable equipment may be a step closer. Oki claims their new MSM6679 voice recognition processor (VRP) has a recognition rate of better than 97 percent. The device operates from either pre-programmed word sets or user-defined vocabularies where customized words are required. Vocabularies are available for standard PC applications such as Windows, Word, and Excel, and for cellular phone applications. A voice prompt or beep verifies that a voice request has been understood. The VRP was designed with CMOS technology, optimized for low-power portable applications. They can easily interface to PC applications via built-in parallel or serial MCU interfaces. The MSM6679 is packaged in an 84-pin PLCC. Unit pricing is $23.50 each in quantities of 10k. Oki Semiconductor, Sunnyvale, CA Contact Avi Zakai: (408) 737-6445.

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Gate array conversion HARD Array (HARD = high area reduction die) is a new production gate array family that uses a silicon area reduction technology to decrease the die size of laser programmable gate arrays (LPGAs) by 50 percent. It is intended for cost-sensitive, high-volume applications. The technology reduces the silicon die area of the production device by bringing all the logic elements of the prototype design closer together, a process called "densification" (or compaction). To decrease prototype to production risk, Chip Express provides specially processed best- and worst-case LPGA prototypes for the user to verify readiness of the design, and assures that the production units operate within those specification limits. HARD Array uses a fine pitch, staggered pad assembly process for all pad limited designs. For higher density, they migrate directly to a triple-layer metal CMOS process. (The 3LM implements a sea-of-gates structure, allowing twice the density of the 2LM process.) Packages include PQFP to 304 pins, and TQFP to 208 pins. BGA packaging is under development. Unit price of the QYH530 (30k gates, 160PQFP) is $9.80 each in 100k quantities. Chip Express, Santa Clara, CA Contact Bob Sandler: (408) 988-2445.

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Prototyping board kits Three new prototyping boards are available for developing highly integrated VLSI and surface-mount circuits. All boards feature power and ground planes, silk-screened signal names on both sides, and pre-defined layout sites for 1206 and 0805 surface-mount components. The boards come in three sizes: a stamp-sized board for assembling single chip circuits, a 3" x 4.5" general purpose board, and a 4" x 8" board with a 16-bit ISA connector. An Engineer's Kit contains 10 boards (three general purpose, three ISA, and four stamp-sized) and costs $129. For a complementary stamp-sized board, send a self-addressed, stamped envelope to Best Proto, Dept. AAE, Box 232440, San Diego, CA 92193-2440. Best Proto, San Diego, CA Contact Steve Rabin: (619) 286-9000.

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Verification system Vampire is a verification system optimized to ensure working first silicon for deep submicron ICs. It is targeted at multi-million transistor circuits using 0.5µm and smaller processes. Cadence claims that their patent-pending "auto-adaptive" technology speeds time-to-market by eliminating design rework and speeding runtimes between two and 100 times. This technology is said to allow Vampire to automatically recognize circuit structure for all design styles and hierarchy permutations, and adapt itself to check the minimum set of unique instances of data. Vampire has been engineered to support Dracula process description files. Vampire is marketed as a modular product. The Layout-vs.-Schematic (LVS) module supports layer operations, device extraction, and netlist comparison, and includes a VampView graphical user interface. Design Rule Checking (DRC) includes layer operations, and a VampView. LVS starts at $75,000, DRC at $85,000, and additional copies of VampView are $15,000. Cadence Design Systems, Inc., San Jose, CA Contact Anne Carr: (408) 894-3429.

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PLL clock generator A new PLL-based clock generator, the S4406Q, provides 12 outputs configured in three banks of four each. Each bank can be individually configured or disabled by standard TTL level signals to allow "green-PC" powerdown functions. The S4406Q can be tailored to individual system clocking requirements. It allows 32 configuration options over a range of output frequencies from 20- to 66MHz. Because of its high drive, low output skew, and low jitter, the S4406Q would be effective for high-performance systems such as Power PC- and Pentium-based servers. Each output can drive 35pF or two to three typical input clock loads. All 12 outputs switch within 500ps of each other, with less than 500ps of jitter. Two or more can be used for systems requiring more than 12 outputs. The S4406Q is housed in a 52 PQFP. It is priced at $9 each in quantities of 10k. Sample parts are available now. Applied Micro Circuits Corp. (AMCC), San Diego, CA Contact: 1-800-755-2622, or (619) 450-9333.

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FPGA design tool Programmable logic device and field programmable gate array designers can use TotalDesigner, the full package with the latest version of CUPL, on the 7000 family of Xilinx erasable programmable logic devices. CUPL version 4.5 supports the XC7000 series of EPLDs and Xilinx's 2000, 3000, and 4000 series of FPGAs. When programming Xilinx FPGA devices, the complete design can be done in CUPL, as all device features can be accessed and specified directly from the CUPL language. The suggested retail price of the CUPL 4.5 package with Xilinx XC7000 fitters in $2,295. Existing CUPL users can upgrade to the TotalDesigner package. Expected shortly is version 4.6, which among other upgraded features will include VHDL support. Logical Devices Inc., Golden, CO Contact Jeff Williams: 1-800-315-7766.

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Back-end tools Integrated Silicon Systems (ISS) has released a series of tools focusing on resistors and capacitors. The first two are HLPE and RCE, intended as the first products in a suite of RC extraction and analysis tools. HLPE is a hierarchical layout parameter extractor that performs full-chip capacitance extraction employing user formulas that enable designers to create custom capacitance extraction equations. Area-based parasitic values, fringe capacitance, and transistor device parameters are extracted, and a hierarchical SPICE netlist is created. RCE, the resistance and capacitance extractor, assists engineers in accurately characterizing critical nets of an IC design. RCE simultaneously extracts resistance and capacitance, allowing designers to extract a distributed RC network, and provides detailed geometric information from selected nets. The other new tool is *Crunch, a resistance and capacitance data reduction tool that makes the combination of parasitic model accuracy and efficient simulation possible. It was developed to manage the increasing data file of complex circuits to improve simulation processing speed while maintaining accuracy. *Crunch runs on Sun, IBM RS/6000, and Silicon Graphics workstations. It is available now and priced between $30,000 and $40,000 depending on configuration. Integrated Silicon Systems (ISS) Inc., Research Triangle Park, NC Contact Casey Jones: (919) 361-5814.

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Transceiver chip A new direct sequence spread spectrum transceiver IC could lower the cost of private ISM band radios from $250-$300 to under $105 for OEMs. The S20043 is a single IC transceiver that can send and receive data at rates to 2Mb/s with direct sequence chipping rates near 64MHz. The transceiver behaves as an intelligent radio peripheral device to a microcontroller. The controller interfaces through common address and data buses, easily monitoring the airwaves and customizing the characteristics of the radio's transmit and receive channels to best use the available spectrum. It also supports bus timing for most popular 8-bit controllers. The IC can control center frequency selection, gain settings, antenna selection, and other configurable characteristics of the radio. A key feature is an integrated slip and track engine on the receiver. It is based on patented technology from Seattle Silicon, and is the first joint product from the AMI/Seattle Silicon partnership formed last June. Product samples should be available in the second quarter. Pricing for 68-pin PLCC package S20043 is $23.50 per unit in 10k volume. American Microsystems Inc. (AMI), Pocatello, ID. Contact Grant Hulse: (208) 234-6964.

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PCB design tool PowerPCB is a constraint-driven PCB design tool that encapsulates shape-based Unix capabilities in an intuitive graphical user interface. It is targeted at electrical and design engineers who need a sophisticated layout tool, but don't want high-priced tools with what they might consider "superfluous" features. Some of the features of PowerPCB are a shape-based PCB editor, standards-based graphical user interfaces; a dynamic route editor, design rules hierarchy, inter-process communications, and multi-mode on-line DRC. A fully-configured PowerPCB system retails for $17,860; other configurations are available. PADS Software Inc., Marlborough, MA Contact Leslie Drohan: (508) 485-4300.

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integrated system design  March 1995