TOOLS AND TECHNOLOGIES

Products and services for system design

IC Design System ArchGen 1.2 is an integrated circuit design system intended to improve multi-partition register-transfer level (RTL) design and design validation vectors (DVV), and reduce the time to develop synthesis-ready data and control path models in weeks instead of months. This version of ArchGen supports multi-partition design for both the top-down and bottom-up design applications. IC developers capture design behavior using a graphical language and validate their designs through a "C" function/performance simulator, graphical animator, and a debugging environment that includes timing diagrams. It is available for Sun SPARCstations running OS 4.1.x, HP workstations running HP-UX 9.0, and IBM RS/6000 workstations. A single floating license is $69,900, and includes a graphical user interface, a function/performance simulator, and a Verilog or VHDL RTL generator. C.A.E. Plus, Austin, TX. Contact Sandhya Shardanand: (512) 338-0165.

CPLD The FLEX 10K family of programmable logic devices features an imbedded array architecture that allows it to implement memory functions with the efficiency of embedded gate arrays. This allows the FLEX 10K family of devices to address designs as large as 100 kgates. FLEX 10K architecture provides two ways of implementing functions: in logic array blocks (LABs), or in embedded array blocks (EABs). LABs and EABs are connected together by an enhanced FastTrack Interconnect scheme (added row lines provide 50 percent more routing resources to the conventional FastTrack Interconnect). The devices will be supported by the MAX+PLUS II development system for PC and workstation platforms. The FLEX 10K family contains seven members, ranging from 10k to 100k usable gates. The EPF10K100, a 100 kgate device with a RAM capacity of 26,624 bits, will be available in the fourth quarter of this year. The EPF10K50, a 50 kgate, 20,480-bit device, will be out in the third quarter. The rest are scheduled for 1996. Altera, San Jose, CA Contact Robert Beachler: (408) 894-7000.

Model development tool The Code Model Software Development Kit, or CM-SDK, is Intusoft's model development kit for a non-proprietary HDL. It allows designers to develop and debug HDL models for use with IsSpice4, the Intusoft SPICE 3 Windows-based simulator. The modeling architecture is called XDL (for extended description language), and is based on XSPICE. XDL is based on the C programming language, and is said to be the only non-proprietary analog and mixed-signal HDL available for Windows. The CM-SDK consists of a compiler and other tools, SDL model source code, include files, and documentation on creating XDL models and interfaces to IsSpice4. The SDK is supported under Microsoft Visual C++ 1.1 or 2.0 under Windows-NT or Windows95. The compiled XDL models may be used with IsSpice4 running under any Windows environment. The CM-SDK is $3,500. It also comes in a bundled version with the ICAP/4Windows simulation system (including the IsSpice4 simulator) for $5,500. Intusoft, San Pedro, CA Contact Charles Hymowitz: (310) 833-0710.

State machine design tool The visual extended state machine design tool BetterStatePro has been augmented to support Mealy Machine design methods. This allows the Extended State Machine to react to input stimuli even without the presence of a clock event. BetterStatePro now allows designers to work with both Mealy and Moore design implementation methods, as the program's automatic VHDL code generator supports both. It also supplies a Visual Basic code generator at no additional cost. Using the Visual Basic code generator, designers can create visual prototypes. The BetterStatePro code drives the logic of simulations, and the diagrammatic behavior can be mapped to one of the target languages (C, C++, VHDL, or Verilog HDL). BetterStatePro can be used on any IBM PC or compatible running MS Windows 3.x. Users have a choice of C, C++, VHDL, or Verilog HDL code generators. The cost is $495. Additional code generators are available. R-Active Concepts, Cupertino, CA Contact Doron Drusinsky: (408) 438-7684.

Verilog Simulator VCSi, incorporating all the features of standard VCS, is Chronologic Simulation's new Verilog simulator. It comes bundled with an interactive interface for debugging design code. The interactive graphical interface presents an analysis and debug environment that includes a design hierarchy window to navigate the design, a waveform display window, and a logic browser. The software is fully compliant with the IEEE Verilog standard and supports all PLI routines specified by the Open Verilog International standard. VCSi is available now for a floating license fee of $20,000. Chronologic Simulation, Los Altos, CA Contact Lisa Schmidt: (415) 965-3312.

Single-chip solution Silicon Systems' new 32P4910 PRML Read Channel offers a high-speed (120Mbps) data transfer rate and enhanced data detection features. With their proprietary analog Viterbi detector and five-tap equalizer, the 32P4910 is said to contain all the functions needed for a single PRML chip Samples of the one-chip read channels are available now in a 100-lead TQFP package. Sample quantities are priced at $16 per thousand. Silicon Systems, Tustin, CA Contact: 1-800-6524-8999, ext. 151.

Mixed Verilog/VHDL Simulator V-System/Plus mixes VHDL and Verilog without the use of two simulators and a backplane. It enables seamless simulation of Verilog and VHDL through a technology called "single kernel simulation" (SKS). With SKS, the combined design simulates with a single event queue. V-System/Plus includes both a Verilog and VHDL compiler, an interactive simulator, and source language debugger. Using multiple interactive windows, designers can simultaneously view and interrogate the design hierarchy, view the Verilog and VHDL source during execution, display variables and signals, control the simulator, display selected processes, and view any combination of VHDL and Verilog signals in the waveform display. V-System/Plus complies with the IEEE VHDL Standard 1076-1993, the OVI 2.0 Verilog Reference Manual, and the OVI 1.0 Programmable Language Interface Manual. (The IEEE P1364 workgroup is currently working on standardizing Verilog.) The program is available for Unix workstation; a Windows version is scheduled for release in the second half of the year. V-System/Plus is $29,995 for a single workstation floating license. Upgrades for users of V-System will be available. Model Technology , Beaverton, OR Contact Robert Hunter: (503) 641-1340.

Gate Array Using a patented laser-based disconnect system, Chip Express can deliver prototype gate array devices in as quickly as a day. The QYH580 has 60k to 70k usable gates, and is the highest density member of the 0.8µm laser programmable gate array (LPGA) family. The QYH500 family is available in 10 to 80 kgates, with up to 396 programmable I/Os, toggle rates up to 600MHz, and NAND gate delay times of less than 300ps. Uses for the QYH580 include complex digital functions in wireless network A/D and D/A system boards, and high-speed networks using ATM or FDDI interfaces. It is available in a broad selection of packages including QFPs (up to 304 pins) and PGAs (up to 299 pins). Standard NRE for the Chip Express QYH580 five-day prototyping service, including two fully tested parts, is $40,000. Unit price for production devices of the QYH580, 160-pin PQFP in 100k-unit quantities is $28 each. Chip Express, Santa Clara, CA Contact Bob Sandler: (408) 988-2445, ext. 148.

Simulator SpeedSim/3 is a fast cycle-based software simulator for verifying digital logic designs. It is intended specifically to overcome performance limitations of event-based simulators, and the high-cost of hardware accelerators. It is said to deliver 10 to 100 times the performance of Verilog-XL with up to 2,000 cycles per second throughput on large design simulation. It uses a proprietary technology called a Boolean Dataflow Engine to fit a 1 million gate design into a 10MB image. This allows engineers to simulate large design on desktop workstations without paging. A SpeedSim/3 option, Simultaneous Test, allows up to 32 different tests to run simultaneously on the same image of a design model. The high-speed compiler technology allows the recompiling of a 1 million gate model in under 10 minutes on a desktop SPARC. SpeedSim/3 uses symmetric multiprocessing technology (SMP), which can deliver near linear performace gains on up to eight processors implemented in a single system. Platforms supported by SpeedSim/3 include Unix workstations from Sun, Hewlett-Packard, and IBM. The base simulator is $35,000 for a single networked-license. SpeedSim, Westford, MA Contact Don McInnis: (508) 692-3737.

EPLD Xilinx has released a fast, high-density erasable programmable logic device, the XC73144. The device has a propagation delay of 7.5ns; Xilinx calls it a record for EPLDs with a density greater than 3,500 usable gates, providing designers with a 25 percent speed improvement over equivalent-size EPLDs. The faster grades of the XC73144 are 100 percent compliant with the peripheral component interconnect (PCI) local bus specification. The device is available in either a 160-pin PQFP or a 225-pin ball grid array to accomodate logic- or I/O-intensive designs. Output drive is specified at a full 24mA, incorporating an I/O interface capable of interfacing to either 3.3- or 5V logic systems. It is supported by the Xilinx ELPD Translator (XEPLD) development software. The XC73144 is available in 7.5-, 10-, 12-, and 15ns speed grades. The 160-pin PQFP version is available at $59.90 each in volumes over 100. The 225-pin BGA version is $77.87 each in volumes over 100. Xilinx , San Jose, CA Contact Vallee Hubbard: (408) 879-5085. *

integrated system design  May 1995