TOOLS AND TECHNOLOGIES

Products and services for system design

DRAM System designers can work with advanced graphics controllers and high-speed CISC and RISC microprocessors now using the µPD481850, a new 8M synchronous graphics RAM (SGRAM) device from NEC. The 8M SCRAM is manufactured using a 0.45µm CMOS process technology. It is organized as 128k words x 32 bits x two banks, and can store 256 colors for a 1,023 x 768 display. The device operates synchronously from a 3.3V power supply at speeds of 66-, 83-, and 100MHz, and has a basic bandwidth of up to 400MB/sec. It also supports low-voltage TTL interface specifications. The µPD481850 is housed in a 100-pin PQFP with a 14mm x 20mm footprint. Samples are $97.40. Mass production is slated for the third quarter of this year, with the cost expected to drop to $35 per unit in 10,000 unit quantities. NEC Electronics Inc., Mountain View, Calif. Contact: 1-800-366-9782.

IC design tool family IC Craftsman is an integrated circuit design software product line that addresses interconnect-sensitive layout issues for high-speed digital, analog, and deep submicron designs. It suits a broad range of IC layout applications including multi-layer top-level chip assembly, device-level layout, critical net pre-routing, and post-route clean-up. IC Craftsman includes an on-line hierarchical rules manager, a connectivity-driven placement and route editing environment, and automatic timing- and noise-controlled routing solutions. There are four products in the IC Craftsman family: Inspector, Apprentice, Journeyman, and Master. Inspector provides placement, timing- and noise-rule checking, violation viewing, and reporting. Apprentice adds to that a shape-based placement and route editor. Journeyman adds to that automatic timing-controlled routing capability and ECO support. Master adds automatic noise-controlled routing features. Network licenses for each run $10,000, $30,000, $70,000, and $100,000, respectively. All IC Craftsman configurations are available on Sun, HP, and IBM workstations. Cooper & Chyan Technology Inc., Cupertino, Calif. Contact Ron Dudzinski: (408) 366-6966.

Datapath design solution The makers of Smartpath say that the datapath design solution reduces datapath die size and wire length by 30 to 50 percent over traditional standard cell and gate array approaches. In a test case, Smartpath placed 8,400 datapath instances and 500 functions in less than four minutes. Smartpath provides the capability to embed the layout of random or control logic within datapaths (rather than implementing such logic external to the datapath). Smartpath's ability to "interleave" datapath functions allows designers quickly to modify the datapath aspect ratio to fit the datapath within global chip specifications. The bus router also supports over-the-cell routing, so bit-swapped buses can be routed without expanding chip size. It leverages existing Preview floorplanning technology and has interfaces to the Composer schematic editor, Verilog-XL, Cell Ensemble, and Cell3 Ensemble for routing. As a building block tool, Smartpath complements Virtuoso Layout Design System. Smartpath is sold as an option to either the Preview floorplanner, Cell3 Ensemble, or Cell Ensemble placement and routing environments starting at $32,000. An optional Datapath Compiler for Verilog is available for $12,500. Cadence Design Systems Inc., San Jose, Calif. Contact Anne Carr: (408) 894-3429.

Synthesis product Synplify is Synplicity's first full-function logic synthesis tool. It supports designs written in VHDL and Verilog HDL and targets multiple leading CPLD and FPGA devices. Synplify is fast; it can synthesize (compile, optimize, and map) the suite of nine PREP benchmarks in less than a minute, and a typical 5,000-gate FPGA in a few minutes. Synplify runs on PC platforms under Windows and Windows NT, and on Unix workstations. The PC version is $8,000; the Unix version sells for $16,000. Single technology versions of the software, called Synplify-Lite, are available for a limited time at $4,000 for PCs and $8,000 for Unix. Those who buy Synplify-Lite can upgrade later to multi-vendor Synplify. Synplicity Inc., Mountain View, Calif. Contact Alisa Yaffa: (415) 961-4962.

Power analysis tool Lsim Power Analyst allows deep submicron designers to "zoom in" on any portion of their IC design for power consumption analysis. The interactive tool also provides diagnostic facilities to aid designers in meeting power constraints. Power Analyst analyzes the design for total power consumption involving switching current, dynamic short-circuit current, and static short-circuit current. Mentor Graphics says that it executes analyses more that a thousand times faster than SPICE can. In addition to power calculation capabilities, it can be used to analyze the analog effects of digital circuits. It operates within the Mentor Graphics Lsim design environment and is priced at $50,000. Mentor Graphics , Wilsonville, Ore. Contact Wendy Eimers: (503) 685-1398.

Component information system Explore-CIS is a component and supplier management system providing design and procurement personnel with desktop access to component, supplier, and reusable design data. Explore-CIS's "soft-model" approach allows users control over underlying data models and lets them customize the database without complex programming or database expertise. The Cascade -Search technology enables users to perform complex searches using properties from multiple object classes; users define search properties for an object and all related objects in a "cascaded" fashion with a single window. Explore-CIS works with leading EDA systems (e.g., Cadence, Mentor , and Viewlogic ). A complementary product is VIP Reference Databases, a family of manufacturer-referenced databases that provides information for the most current and important parts from over 200 leading electronic component vendors. The cost ranges from $75,000 for 10 users to multi-million dollar global enterprise implementations. Aspect Development Inc., Mountain View, Calif. Contact Craig Palmer: (415) 428-2700.

Data reporting service A new quarterly publication, Market Statistics Service (MSS), provides aggregate revenue and license information collected from 80 to 85 percent of the companies in the EDA industries. MSS is a service of the Electronic Design Automation Companies (EDAC). Its uses include market research, establishing industry-wide projections, and market trend analysis. The information is on software licenses (and application-specific hardware systems) and corresponding sales revenues. EDAC will report only aggregate data, thereby protecting the confidentiality of each company's shipment data. MSS is not run for a profitable return. Subscriptions start at $2,500 per year. Discounts are provided to EDA companies that also participate by reporting data. EDAC, San Jose, Calif. Contact Evelyn Gurzi: (408) 287-6371.

Microcontrollers Additions to the COP8 family of embedded controllers add analog functionality, hardware multiply and divide, and low-cost functionality to that line. This expands the number of applications for which the 8-bit microcontrollers can be used. The availability of a low-cost Evaluation and Programming Unit allows designers to become familiar with basic COP8 devices quickly. The COP888EK integrates an analog function block for applications requiring analog-to-digital controller functions. The COP888GW is the first 8-bit microcontroller to include built-in hardware-based multiply and divide functions, making it useful in such applications as fuzzy logic and digital signal processing. The COP912 is a low-cost version of the COP8, breaking the 50¢ per unit (in quantities) barrier. The COP8 Evaluation and Programming Unit is a low-cost in-circuit simulator that enables programmers to debug code and hardware designs for Basic Family COP8 microcontrollers quickly. The COP888EK is $4.00 each in 10,000 quantities of ROM-based devices in PLCC packages, and $9.25 each for 500 of "one-time programmables." The COP888GW is $6.75 each in 10,000 quantities in PLCC packages. The COP912 is $0.49 each in 1 million piece quantities, $0.65 each in 10,000 quantities. The COP8 EPU is $135 complete. National Semiconductor Corp., Santa Clara, Calif. Contact Michele Holguin: (408) 721-2880.

DSP development system MightyMight 56002 (MM56002) is a dual purpose, general DSP system. It is a low-cost PC-based DSP56002 development system, and it serves as an embedded system. The compact (3.5" x 2.1") DSP56002 module from the MM56002 system can be embedded in different applications. The MM56002 features a Motorola processor running at 40MHz with 20MIPs, 96kB of zero-wait state static RAM, and supports 32kB of EEPROM on board. It has an RS-232 interface. BNK Electronics Inc., Englewood Cliffs, N.J. Contact Ferdinand S. Kim: (201) 894-5905.

FPGA Crosspoint Solutions has announced the second member of its CP20K family of FPGAs. The new device, the CP20840, has 8,425 available gates and offers a 30 percent speed improvement over similarly dense programmable logic devices. It uses a channeled gate array architecture compatible with industry standard mask programmable gate arrays, and is manufactured in a 0.8µm process using dual-layer metalization. The I/O buffers have CMOS, TTL, Schmidt trigger and pull-up inputs, and provide 4mA, 8mA, tri-state, open-drain, open-source, and slew-controlled outputs. According to Crosspoint, in a typical application the CP20840 would utilize between 5,000 and 6,000 gates and operate at 30- to 50MHz. It is offered in a ceramic pin grid array and a plastic quad flat pack. In quantities over 100, the 299-pin CPGA is $467 each, and the 208-pin PQFP is $373. Production quantities will be available in July. Crosspoint Solutions Inc., Santa Clara, Calif. Contact Michael Levis: (408) 988-1584, ext. 203.

Gate array to PLD converter Altera's new gate array to programmable logic conversion kit allows designers to take existing or future gate array designs and convert them to Altera programmable logic devices. Designers need not alter their existing design flow to use the conversion kit. They can begin by designing for their target gate array vendor using the vendor library. Altera then takes a post-synthesis netlist of the design in EDIF format and reads it into its MAX+PLUS II software. The Altera Gate Array Conversion Kit is available for LSI Logic and Fujitsu now. Translation libraries to support other vendors are being developed. Altera, San Jose, Calif. Contact Robert Beachler: (408) 894-7000.

FPGA toolset After two years of development, Actel has announced the Designer Series 3.0 FPGA design toolset. The new suite of tools features a graphical user interface and an object-oriented database aimed at eliminating much of the learning curve for complex FPGA designs while allowing full performance. The DirectTime option allows the development of fully deterministic FPGA designs. Such tools as PinEdit and DesignScript help make the package easy for designers to use. PinEdit provides a graphical representation of the FPGA package and allows a drag-and-drop placement of signals on selected pins, while DesignScript provides a macro language allowing users to run the design process as a batch command. Designer Series 3.0 was developed in C++ and geared to run with Windows 3.1, Windows for Workgroups, Windows NT, and Windows 95. The basic Designer Series 3.0 supporting gate counts to 2,500 sells for $995. Designer Advantage 3.0 handles gate counts across a whole range of capacities and cost $2,495 for the PC version and $3,495 for the workstation version. Current Actel customers who subscribe to Actel's support/update program will receive Designer Series 3.0 free of charge. Actel Corp. , Sunnyvale, Calif. Contact Larry Blessman: (408) 739-1010.

PLD programmer XPGM is a low-cost programmer exclusively for Xilinx EPLDs and SPROMs. The XPGM programmer resides inside a PC, taking advantage of the computer's processor. It then connects to an external adapter socket via a 30-inch ribbon cable. The XPGM can program the larger members of the Xilinx XC7000 family (e.g., the XC73108) in nine seconds on a 50MHz 486 PC. The $295 price includes adapters for programming XC7300 EPLDs in 44-pin PLCC packages and XC1700 SPROMs in 8-pin DIP packages. Other adapters are available ranging from $99 to $199. Deus Ex Machina Engineering, St. Paul, Minn. Contact: (612) 645-8088.

Verilog testbench development tool TesTech is a Verilog tool that aids designers in the development of specification-based simulation testbenches for verification and test of complex ICs. TesTech links Summit Design's TDS (a graphical timing-specification tool) with its Visual HDL (a graphical HDL specification tool), creating Verilog testbenches that check conformance of circuit timing to design specifications. It uses standard databook format to describe timing requirements, and automatically integrates timing templates with test pattern data in the resulting testbench. The Tester Rules Checker (TRC) option analyzes testbenches for compatibility with targeted automated test engineering equipment from vendors such as LTX, ý Schlumberger, and Teradyne. TesTech is $20,000, and the TRC option is $10,000. Summit Design Inc. , Beaverton, Ore. Contact Daniel Skilken: (503) 643-9281.

Design software The XACT 6.0 Software Development System is billed as the answer to designers' "time-to-volume" problem. Fast implementation and debug cycles, and a short learning curve are part of the solution. Xilinx has also added six power tools that can be accessed through a new graphical user interface. The features include: Design Manager, which provides version control, device retargeting, and design re-use; Flow Engine, which allows control over the implementation process; and PROM Formatter, which simplifies device configuration and daisy chaining. The software will initially support six Xilinx device families: XC2000, XC3000, XC3100, XC4000, and XC5000. XACT 6.0 should be available in August. It will run on PCs operating under Windows 3.1. Hewlett-Packard and Sun Microsystems workstation versions will be available after October. New user prices range from $995 to $4,595 for the PC version, and $7,995 for the workstation version. Current users of XACT under a Xilinx support or maintenance plan may upgrade to XACT 6.0 for free. Xilinx Inc. , San Jose, Calif. Contact Vallee Hubbard: (408) 879-5085.

PCB design tool VeriBest PCB 14.0 is the latest version of Intergraph's software tool for the automatic design of high-density, mixed-technology printed circuit boards and laminate multi-chip modules. Improvements include several high-speed design and signal integrity features, blind and buried vias, dynamic moving and routing of components, automatic bus routing, and controlled-pattern delay tuning. VeriBest PCB 14.0 is intended to offer workstation power for PC users, and is designed for PCs operating on Microsoft Windows NT, but it has also been ported to Unix to provide users a choice of operating systems. The cost of VeriBest PCB 14.0 is $30,000. Orders are now being taken; it will begin shipping on August 1. Intergraph Electronics, Huntsville, Ala. Contact: 1-800-VeriBest (1-800-837-4237).

PC semiconductor simulator Device Wizard is semiconductor simulation software for those who prefer to work with PCs and with software designed for PCs rather than ported over from Unix-based machines. The tool can simulate the electronic, thermal, reliability, and optical preferences of modern semiconductor devices. Typical devices include submicron MOSFETs, MESFETs, power devices, programmable devices (e.g., EPROMs), etc. Device Wizard includes predefined templates for over 20 common semiconductor device types, and has calibrated material libraries for silicon, GaAs, and other materials. Device Wizard's base price is $12,000 per computer. It is available for PC compatible computers (386, 486, and Pentium) with an internal or external floating point processor and MS DOS 5.0. It is also available for Unix computers with emulation software (Soft Windows) installed. Dawn Technologies Inc. Contact Jerry Erickson: (408) 737-6181.

Enhanced EDA software package QuickLogic has announced the new QuickTools 5.0 development software package, which enhances third-party design environment productivity for the pASIC 1 family of FPGAs. The package also bundles the new version of QuickLogic's SpDE tool. SpDE 5.0 adds design support for QuickLogic's newest devices, including the 8,000-usable-gate QL24x32B, and the upcoming 3.3V versions of the pASIC 1 family members. Two new FPGA design automation capabilities included are a secondary level of logic optimization, and automatic optimal buffer insertion for high fan-out signal paths. QuickTools works on Hewlett-Packard workstation platforms, PC compatibles running Windows or Windows NT, and on Sun workstations. PC versions are $995. Sun and HP platform versions are $1995. Existing customers under software warranty or maintenance agreement for the SpDE product are being sent upgrades at no cost. QuickLogic Corp., Santa Clara, Calif. Contact Ed Smith: (408) 987-2000.

Cycle-based software simulator SpeedSim/3, a fast cycle-based software simulator for verifying digital logic designs, is designed specifically to overcome what SpeedSim views as performance limitations of event-based simulators and the high cost (and inflexibility) of hardware accelerators. SpeedSim/3 uses a proprietary technology called a "Boolean Dataflow Engine" to fit a 1 million gate design into a 10MB image, allowing design engineers to simulate large designs on desktop workstations. It also means more and quicker tests than event simulators can run. Simultaneous Test, a SpeedSim/3 option, allows up to 32 different tests such as diagnostics or application program streams. SpeedSim/3 platforms include Unix workstations from Sun Microsystems, Hewlett-Packard, and IBM. A single networked license is $35,000. SpeedSim Inc., Westford, Mass. Contact Don McInnis: (508) 692-3737.

VITAL libraries Mentor Graphics has announced VITAL (VHDL Initiative Toward ASIC Libraries) library support from 12 ASIC and programmable logic vendors (a total of 61 technologies) for its QuickVHDL simulator. VITAL libraries are available from Altera, AMI, AT&T Microelectronics, Fujitsu, IBM, Oki Semiconductor, UTMC, VLSI Technology, and Xilinx . In months to come, Actel , Honeywell, and LSI Logic libraries will be made available as well. QuickVHDL was the first VHDL simulator to offer VITAL-based simulation capability and VITAL acceleration. It includes accelerated VITAL support as a standard feature. It is available on Sun SPARC, Hewlett-Packard, and IBM hardware platforms. The software is priced at $14,950 per floating license. Mentor Graphics Corp. , Wilsonville, Ore. Contact Laura Barber: (503) 685-1809.

Front-end tool Visual Software Solutions has added Verilog to its StateCAD line. StateCAD translates bubble diagrams into synthesizable OVI-compliant Verilog for tools from FrontLine, Simucad, and Exemplar. Diagrams are specified graphically, analyzed for design problems, then translated to synthesizable HDL. Support includes one-hot and encoded state assignment, area and speed code optimizations, synchronous/asynchronous reset, and Mealy/Moore outputs. StateCAD allows code to be generated in Abel, Verilog, CHDL, and C. HDL targeting allows the appropriate language to be used for a device (e.g., Abel for PALs and CPLDs, Verilog or VHDL for FPGAs and ASICs). Designers can switch among languages with a button click and regenerate the code in seconds. The StateCAD Verilog Edition is $1,495, as is the VHDL Edition. The Abel Edition is $995. The C Edition is free with any StateCAD purchase to July 1. Visual Software Solutions Inc., Coral Springs, Fla. Contact (305) 346-8890 or 1-800-208-1051.

ATM transceiver Vitesse Semiconductor's low-cost VSC8110 622Mb/s SONET/ATM transceiver combines serialization and de-serialization functions with a fully monolithic Clock Multiplier on a single integrated circuit. It has been designed to meet the emerging ATM User Network Interface (UNI) standard. The clock is selectable for 155- or 622MHz operation. The device can be used with 19.44-, 38,88-, 51.84-, or 77.76MHz external reference clocks. By generating a constant 51MHz clock, the VSC8110 eliminates the need for separate clock generation circuitry to clock other components. The device is manufactured with Vitesse's mature H-GaAs III 0.6µm process. It is packaged in a 100PQFP with integrated heat spreader. Production pricing is $52 each in 1,000-piece quantities. Vitesse is working with Hewlett-Packard and PMC-Sierra to develop a complete solution for ATM applications using the VSC8110. Vitesse Semiconductor Corp., Camarillo, Calif. Contact: (805) 388-3700.

integrated system design  June 1995