TOOLS AND TECHNOLOGIES

Products and services for system design

Development tool The Designer Series 3.0 development series features a graphical user interface and an object-oriented database intended to eliminate the learning curve for complex FPGA designs and maximize performance. The graphical design flow manager is a new feature that steps the user through the design. Another new feature is DesignScript, a feature that provides a macro language allowing users to run the design process as a batch command, saving the user steps such as compile, place, route, fuse, extract, etc. All these new features are possible because of the new object-oriented database (licensed from Object Design), which tracks design details during execution. With the DirectTime option, the Designer Series 3.0 allow the development of fully deterministic FPGA designs. Unlike tools relying on manual placement, DirectTime is said to ensure that pre-route specified timing delays are accurately represented in the final design. The basic Designer Series 3.0 system supports gate counts to 2,500, and sells for $995. Designer Advantage 3.0 handles gate counts across the whole range of capacities and costs $2,495 in PC version and $3,495 for workstations. The DirectTime option sells for $995 for both PCs and workstations. Actel Corp. , Sunnyvale, CA. Contact Larry Blessman: (408) 739-1010.

PC/104 module The PC104i is a PC-compatible single-board computer in a single stack PC/104 form factor using the S-MOS CARDIO family of single board computers. It measures 3.6" x 3.8". The PC104i could be used in electronic medical systems, automobiles, communications systems, machine and process controllers, and any other applications that have traditionally been designed using embedded control-based microcontrollers. To upgrade from an x86 to a 386 or 486, one need only replace the S-MOS CARDIO module with another. The PC104i is the result of a cooperative effort between S-MOS Systems and Intelec Technologies. Pricing for the PC104i starts at $290 in quantities of 100, while pricing for the S-MOS CARDIO-486 starts at less than $800 in quantity, and less than $400 for the 386 version. Pricing is dependent on memory and other system configuration requirements. S-MOS CARDIO evaluation kits range from $900 to $2,300 depending on components (memory, LCD panel, hard or floppy drive or both, etc.). S-MOS Systems Inc., San Jose, CA. Contact marketing: 1-800-228-3964.

DSP library A new commercial DSP library for FPGAs enables the processing of real-time video data streams in the Spectrum system. Up to 1,350 DSP MIPS equivalent performance can be achieved in two XC4010 FPGAs for gray scale image morphology applications. Two can also deliver 400 DSP MIPS sustained performance. These MIPS allow processing NTSC video in real time using a 16 Tap Linear Filter, two nine Tap Binary Filters, etc. The primary benefit is the elimination of the Von Neuman architecture used in DSP chips. Additional DSP functions can be implemented rapidly, and libraries can be created, by using XC Compiler, a C syntax HDL. For more information, contact the manufacturer. Giga Operations, Berkeley, CA. Contact Ron Higgins: (510) 528-8438.

Workstations Hewlett-Packard's HP 9000 J-Class workstations have dual processor capability. The new 960MB/sec memory bus is said to be three times the speed of current systems. The J-Class can be configured from 32 Mbytes to 1 Gbytes of RAM, with up to 4 Gbytes internal fast/wide SCSI-2 hard drives. Graphics capabilities are from simple 2-D to virtual reality (fast 3-D graphics with new architecture based on the PA-RISC floating point). The J200 operates at 100 MHz and the J210 is 120 MHz. Pricing starts at $32,775. Hewlett-Packard, Los Altos, CA. Contact marketing: 1-800-452-4844.

Electromagnetic simulator Designers of RF and microwave components have a three-dimensional high-frequency electromagnetic simulator in the High-Frequency Structure Simulator (HFSS). Version 4.0 of HFSS includes four new features to extend the range of solutions available to design engineers. With these features, designers can analyze antenna parameters, use new voltage and current gap sources that allow easier excitation of structures, specify a range of plane wave excitations that can be used with radar cross section plots, and characterize anisotropic dielectric materials such as sapphire and GaAs. Further enhancements in v4.0 include one to the user interface, allowing the ability to plot Smith charts, and the availability of a network-licensed version of the software. The cost of HFSS is $41,800. Network-licensed versions are available on a variety of popular Unix-based workstations. Hewlett-Packard EEsof, Westlake Village, CA. Contact marketing: 1-800-452-4822.

EDA tool The Epilog-XL multi-mode timing verification tool gives designers flexibility in debugging the timing of ASIC-based designs (especially submicron designs). Epilog-XL combines the capabilities of static timing analysis with Verilog or spread-delay gate simulation. Designers can check the timing of all parts of a design's logic in one operation. By combining the two capabilities, Nextwave says, designers no longer have to wait days for a full simulation run just because part of the design requires detailed timing simulation. The tool's reverse synthesis function automatically builds high-level behavioral timing models from Verilog descriptions, a function that is said to make it easy to move between simulation and timing analysis. Epilog-XL will be available in the third quarter. Epilog-XL is designed for Sun SPARCstations and IBM RS6000 workstations using the MOTIF graphical user interface. A single node-locked license is $35,000. Nextwave Design Automation, San Jose, CA. Contact Hal Daseking: (408) 437-3933.

System design methodology BoardQuest is a highly automated engineering environment with tools for high-speed systems engineers who need to optimize system performance across multiple domains simultaneously. These domains include timing, signal integrity, electro-magnetic interference, etc. BoardQuest merges functional and physical system design abstractions, allowing engineers to characterize and refine their design performance as they make partitioning decisions across an entire multi-board system. The engineering floorplan is initiated from a bill of materials, a schematic netlist, or by selectively reusing physical elements and performance constraint sets. Components can be created on the fly for floorplanning and engineering analysis without library dependencies. Timing data is imported through standard delay files and used to guide critical component placement and interconnect. A special feature of BoardQuest is SigXplorer. It allows engineers to perform ASIC/IC I/O buffer design for managing timing across system packaging and interconnect levels. With the tool engineers can also develop behavioral models of net topologies and termination strategies for critical signals, and encapsulate them in topology template libraries without worrying about implementation details. BoardQuest runs on standard Unix workstations and servers from Sun, HP, and IBM. It is available in targeted product configurations starting at $19,000. Cadence Design Systems Inc., San Jose, CA. Contact Laurel Stanley: (508) 262-6104.

Microprocessor The 110-MHz MicroSPARC-II is Sun's newest member of the general purpose microprocessor family. The MicroSPARC-II is used extensively in desktop and computing applications. It is pin-compatible with its 70- and 85-MHz predecessors, and requires no application or operating system changes, allowing customers an easy upgrade path for higher performance. Initial pricing for the 110-MHz MicroSPARC-II processor is $649 each in thousand-unit quantities. Sun Microsystems Inc., Mountain View, CA. Contact marketing: (415) 960-1300.

BIST tool LogicVision has just announced the first tool with complete built-in self-test (BIST) at the IC level. ICBIST couples front-end generation of synthesizable RTL code for logic BIST, RAM BIST, and JTAG/1149.X, with back-end tools for BIST analysis and testability insertion. BIST techniques may be selectively applied in a hierarchical and unified manner to generate test solutions. The test solutions developed for the ICs simplify re-use for board, system, or field test diagnosis. The ICBIST product is available now with costs of $140,000 per seat. LogicVision, San Jose, CA. Contact Patrick Scoggin: (408) 453-0146.

FPGA The GateField GF100K family of 100 kgate field-programmable devices combines Flash-based switch technology and a "Sea-of-Tiles" architecture for an increased gate density over competitive offerings. The company also boasts of lowered costs and reduced time to prototype, along with enhanced ease of use. The Sea-of-Tiles architecture, which models the characteristics of CMOS gate arrays, is between two and four times smaller and 20 to 25 percent faster than SRAM-based products in applications from 20 to 40 MHz. The Sea-of-Tiles offers three types of routing resources: one is for connecting logic functions to implement a macro cell, the second is for interconnecting macrocells, and the third is for global signals. The GF100K family consists of six devices ranging in gate capacities from 9,000 to 100,000. They will be offered in a variety of packages including PLCCs, PQFPs, CQFPs, and CPGAs. The family can be programmed with the GateField Desktop Foundry. The initial offering, the GF9K array, will be priced less than $30 each in quantities of 25,000 units. GateField, Fremont, CA. Contact Lyle Smith: (510) 249-5757.

DSP core SGS-Thomson's new D950-CORE fixed-point DSP core was built in its 0.5µm, 3.3V, triple-level metal, HCMOS5 technology. The device is a 40MIPS/25ns 16-bit DSP core that is fully compatible with SGS-Thomson's 0.5µm ASIC technology. The D950-CORE can access three different memory locations per instruction cycle and thus simultaneously perform numerous functions that require several machine cycles with other processors. It includes support for floating-point processing as well as multi-precision operation. An emulation and test unit is included on the core. Major hardware features include a power-down mode, two 40-bit accumulators, a bit-reversed addressing mode, the ability to nest up to three hardware loops, and a co-processor interface with co-processor dedicated instructions to speed up the DSP core. The D950-CORE is available for less than $10 in volume, depending on applications. SGS-Thomson Microelectronics, Lincoln, MA. Contact Peter Uehlecke: (617) 259-2516.

MCU WSI has introduced a family of 2.7- and 5-V, zero-power field-programmable microcontroller peripherals. The ZPSD3XX devices provide a subsystem of logic and memory for microcontroller-based applications which includes up to 1 Mbyte of EPROM, 16 kbytes of SRAM, a programmable address decoder that can access an addition 2 Mbytes of program store, a security bit to prevent reverse-engineering, and a programmable interface to any 8- or 16-bit microcontroller. These MCUs were developed to extend battery life, and can be powered off. The EPROM SRAM, and programmable address decoder in the ZPSD peripherals were implemented using WSI's Integrated Power Management zero-power architecture, allowing them to consume no power unless they are being accessed. The 2.7-V version typically consumes 1µA standby and 1.6mA when operating at 2 MHz. Estimations are that the device could increase cellular phone battery life by as much as three hours. ZPSDs are designed using PSDsoft for Windows, using ABEL for logic design and Simucad's Silos III Verilog simulator. ZPSDs are available in three EPROM densities, in both 5- and 2.7-V operating voltages. Packages include 44-pin ceramic and plastic surface-mount packages, 52-pin PQFP and 44-pin TQFP. Prices start at $5.97 per unit in quantities of a thousand for the ZPSD311-15J (256 kbytes EPROM, 5V, 150ns, OTP PLCC). WSI Inc., Fremont, CA. Contact Dale Prull: (510) 498-1723.

FPGA QuickLogic is shipping 3.3-V versions of its pASIC 1 family of devices. These devices consume approximately a third of the power of a 5-V device and can run counters at over 80MHz. In standby mode, they typically use only 250µA. Interface with 5-V CMOS, NMOS, and TTL devices is supported while operating at 3.3 V, as I/O pins are designed to sink up to 12mA. Designs can be entered and simulated using QuickWorks 5.0. The series includes 1k, 2k, and 4k usable gate devices. An 8k usable gate version will be out in the third quarter. Two speed grades are being introduced, as well. Contact QuickLogic for more information. QuickLogic Corp., Santa Clara, CA. Contact Ed Smith: (408) 987-2000.

Oscilloscope The LeCroy 9370 family of digital storage oscilloscopes has an analog bandwidth of 1 GHz. They feature 500MS/s single-shot A/D conversion per channel, with 2GS/s in single channel mode (for the four channel version). The 9370 family has an acquisition memory of up to 2 million points per channel, with a maximum of 8 million points in single channel mode (again for the four channel version). There are six models in the family, three with two channels and three with four. Depending on which of the six models is used, application areas could be high-energy physics research, industrial electronics, lasers, LAN, telecommunications, semiconductor design and test, magnetic media, power supply design, and broadcasting. All are supplied with LeCroy's ProBus Intelligent Probe Interface. Pricing begins at $11,490 for the 9370 (2-channel, 1 GHz DSO; 1 GS/s Max, with 100k memory), to $26,990 for the 9370L (4-channel 1 GHz DSO; 2GS/s Max, 8 Mbytes memory). Also available are several optional packages. LeCroy, Chestnut Ridge, NY. Contact Mike Lauterbach: (914) 578-6020.

integrated system design  July 1995