TOOLS AND TECHNOLOGIES

Products and services for system design

Sound chip Those needing a DSP-based sound IC have an option with the CM82C650. It was designed with such applications as PC sound cards, sound modules, karaoke systems, keyboards, and digital pianos in mind. The DSP architecture includes a built-in PCM sound algorithm, which can be controlled with variable parameters by the user. Additional peripheral functions provide a low-cost solution for multimedia PC audio operations. Special features include a game port, CD-ROM interface, and the PC interface. It also provides a DRAM interface function. It has a sampling rate of 22 kHz to 46 kHz, and can support the production of 128 distinctive variations of instruments and sounds, including piano, percussion, organ, guitar, synthetic effects, etc. The CM82C650 is provided in a 100-pin PQFP package. Price per unit at 1,000-unit volume is $15. LG Semicon America, San Jose, CA Contact Arun Kamat: (408) 432-5000.

Front-end tool SiliconQuest is a design planning environment for front-end designers of complex ASICs. It features what Cadence calls "the industry's first" technologies for RTL-level, timing-driven ASIC floorplanning and analysis for silicon-based logic. Integrating SiliconQuest with BoardQuest enables design teams to trade off and communicate constraints across both silicon and systems. Critical requirements (e.g. maximum propagation delay on a critical signal I/O) are generated by the system designer within BoardQuest and passed to SiliconQuest to ensure that the ASIC can be easily integrated within the target board or system. SiliconQuest is available in configurations starting at $25,000. Support functions such as QPlace, Silicon Synthesis, and Pearl Timing Analyzer are available separately. A SiliconQuest Quick Start basic package starts at $15,000. It supports industry-standard Unix workstations. Cadence Design Systems, San Jose, CA Contact Mike Sottak: (408) 428-5036.

Coprocessor FPGA Xilinx has unveiled a new architecture for a new class of FPGAs for coprocessing applications. The SRAM-based devices are microprocessor-compatible FPGA coprocessors designed for the embedded control market, hitherto dominated by the ASIC or multi-CPU solutions. Embedded control applications include high-bandwidth and compute-intensive applications such as laser printers, video and image processing systems, telecommunications equipment and encryption/decryption, etc. The XC6200 family features a standard microprocessor interface, unlike conventional FPGA architectures. It also offers a memory-mapped I/O interface (termed "FastMap"). Fast reconfiguration of the entire chip can be performed in less than 200µs. Another key feature is distributed memory; the XC6200 can be used for either logic or memory. With distributed memory, a 16,384-cell device can provide up to 32,768 bytes of memory. Initial offerings will range in density from 9,000 to 55 kgates. Xilinx , San Jose, CA Contact Ann Dennis: (408) 879-4726.

Multiprocessor board The SKYbolt II multiprocessor VME64 board combines 320MFLOPS of multiprocessing performance with the SKYchannel 320 Mbytes per second packet bus. It provides an optional I/O interface through an expansion connector directly linked into the SKYchannel onboard bus. With this connector, a daughtercard with the SKYburst parallel I/O interface may be added without sacrificing compute processors. For P2 interfaces, SKY provides a choice of either 40 Mbytes per second VSB or 320 Mbytes per second SKYchannel connections, delivering up to 3200 Mbytes per second aggregate throughput within a common chassis. The SKYbolt II uses the SKYvec Software Development Environment. SKY Computers, Chelmsford, MA. Contact Dianne Capps: (508) 250-1920.

PC chipset Cypress's hyperCache Chipset for Pentium-class computers is being touted as the industry's first PC core logic chipset with integrated second-level cache. In addition to providing second-level cache and cache tag, the hyperCache Chipset includes a DRAM controller supporting both fast page mode and extended data out (EDO) DRAMs. The chipset integrates key peripherals, including local bus IDE with master mode, keyboard and mouse control, DMA interrupt control, and real-time clock with extra CMOS RAM. Both PCI and ISA busses are supported. The chipset consists of three chips: the CY82C691 PCI and memory controller, the CY82C692 datapath chip with integrated cache, and the CY82C693 peripheral controller. An optional fourth chip is a 16k x 64 cache RAM, which interfaces seamlessly to support large cache sizes up to 1 Mbyte. The three chips in the chipset all come in 208-lead PQFP packages. The chipset integrates 128 kbytes of second-level cache and is $48 each in 1,000-unit quantities. The four-chip chipset, including the CY82C694, packaged in a 128-pin TQFP, offers 256 kbytes of second-level cache, and is $62 in 1,000-unit quantities. Cypress Semiconductor, San Jose, CA Contact Don Parkman: (408) 943-2817.

Reprogrammable memory Atmel has delivered the first two of a new family of reprogrammable memory devices for configuring in-system programmable FPGAs. The reprogrammable EEPROM devices are used to reconfigure SRAM-based FPGAs from Atmel, AT&T, and Xilinx . The "Configurators" (or FPGA Configuration Memories) can be programmed and operate in both 3- and 5-V systems. They are compatible with industry standard two-wire serial interfaces, support up to 10 MHz configuration rates, can be cascaded to support additional configurations, future higher density arrays, and can be programmed in-system or in standard memory programmers. The first devices in the family the AT17C65 and the AT17C128, are 64 kbytes and 128 kbytes respectively. The AT17C Series is compatible with the Atmel AT6000 family, the AT&T 3000 series, and the XC2000, 3000, 4000, and 5000 FPGAs from Xilinx . Atmel, San Jose, CA Contact Joel Rosenberg: (408) 436-4290.

Statistical analysis tool WaferMAP is a graphical and statistical analysis tool designed to identify wafer fabrication and testing problems. Users create a topographical analysis of the entire wafer or a composite of multiple wafers based on each individual die's data. The tool identifies manufacturing process glitches such as non-uniform wafer processing, mask or reticule problems from different layers, or wafer probe processing problems. A node-locked or floating single-user license is $8,800. Innovative Data Solutions, Foster City, CA Contact John Bateson: (415) 349-0500.

Silicon evaluation module The V6502-PCB is VAutomation's silicon evaluation module. The V6502 Synthesizable VHDL 8-bit microprocessor core has been synthesized into two different Xilinx FPGA families: XC4013 and XC5210. The V6502 evaluation modules allow developers to verify their software in real time using actual silicon, avoiding the expense of and ASIC NRE. The modules can be customized to include application-specific logic. The V6502-PCB ($1,500) is available now. The kit includes to complete documentation package for the V6502 Synthesizable HDL core. The core is available for $15,000 in netlist or $75,000 in VHDL source code form. VAutomation, Nashua, NH. Contact Eric Ryherd: (603) 882-2282.

CBIC device Hitachi America's new HG72C series of cell-based ICs can incorporate a wide variety of cells, including an SH-1 series 32-bit RISC microcomputer core. This microcomputer core is a version of Hitachi's SuperH RISC engine. The SH-1 core allows system designers to use HG72C series CBICs to produce single-chip or minimum-chip implementations of wireless, PDA, set-top box, and other high-volume personal access products. SH-1-based designs with 100-kgate logic circuits operating at 20MHz can meet the 1W dissipation limits of low-cost QFP packages, and designs combining the standard SH-1 microcomputer functions and up to 250-kgate circuits can be handled by 2.5W QFPs. The HG72C library includes various timers, serial interface, DMA controller, level shifters, and a span of compiled or diffused RAM and ROM sizes (and EPROM in the future). Production orders will be taken starting in October. A typical 100-kgate device with an SH-1 core will cost approximately $25 in 10k-unit volume. Hitachi America, Semiconductor and IC Division, Brisbane, CA Contact: 1-800-285-1601, ext. 33.

Analog circuit optimizer MicroSim has introduced PSpice Optimizer, v.6.2. The analog circuit optimizer is said to improve analog and mixed-signal design performance while reducing engineering time by over a third. Example applications include: in discrete designs of amplifiers (gain, power consumption, phase margin), power supplies, high-voltage switches, and filters; in IC amplifier design, filters, A/D and D/A converters, and cells, etc. PSpice Optimizer for Windows is $2,989 ($3,900 for the international package). For Sun-OS, the PSpice Optimizer is is $3,900 ($5,100 internationally). Engineers can save $1,089 if they purchase PSpice A/D and PSpice Optimizer for Windows together in their initial purchase. MicroSim, Irvine, CA Contact Janet A. Roberts, (714) 770-3022, ext. 239.

ASIC NEC's low-power ASIC family CMOS-8LHD has cell-based array (CBA) architecture, delivering densities approaching cell-based products with the low development costs of gate array products. The 3.3V gate arrays use a three-layer metal 0.5µm drawn CMOS process. The CMOS-8LDH has 12 base arrays, ranging from 75k to 1.12 million raw gates. The I/O architecture is optimized to ensure that only one I/O slot is required to support popular interface standards. Interface types include 5V PCI, 66 MHz PCI, and LVTTL and slew rate buffers. A library release scheduled for this fall will include FTL buffers, HSTL buffers, and pseudo-ECL buffers for high-speed clock inputs. CMOS-8LHD supports NEC's design environment, OpenCAD, and the technology is supported at a variety of NEC fabs. Packaging will include PQFP in pin-counts up to 304 pins, and BGA packaging with up to 480 balls. Typical cost is an NRE plus unit prices of $10 to $150 in lots of 10k. NEC Electronics, Mountain View, CA Contact: 1-800-366-9782.

Front-end tool The Electronics Workbench Engineer's Pack offers design engineers the ability to design and verify complex circuits using Electronics Workbench's mixed-mode simulation and then integrate these circuits into SPICE and PCB design automation software. The Engineer's Pack comes with over 2,450 models, including 500 transistors, 500 diodes and thyristors, 500 op-amps, and 600 FETs. The SPICE I/O utility allows users to export Electronics Workbench schematic files to SPICE netlist format, as well as read files from other SPICE simulators. The PCB Export utility offers the ability to export schematics directly into most popular PCB layout packages, automatically remapping the file conversions for OrCad, Tango, and other popular PCB netlist formats. The Electronics Workbench Engineer's Pack is available for DOS, Windows, and Macintosh operating systems. The cost is $599. Interactive Image Technologies, Toronto, Ontario, Canada. Contact Sheldon Kerzner: (416) 977-5550.

EDA software CD-ROM MicroSim has released EDA evaluation software for Windows and a complete set of on-line manuals on CD-ROM. The release allows designers to evaluate MicroSim's family of Windows EDA systems free of charge before they buy. The CD-ROM features the EDA software (full-featured, albeit limited to small designs only), tutorials, multimedia slide shows, and complete on-line manuals. The software available on the CD-ROM includes MicroSim Schematics, MicroSim PSpice Optimizer, and MicroSim Polaris, etc. The CD-ROM evaluation software is being given free to engineers who want to "test drive" MicroSim software before making purchasing decisions. MicroSim, Irvine, CA Contact Janet A. Roberts: (714) 770-3022, ext. 239.

HDL entry system SpeedCHART is a graphical HDL design entry system for high-level system, IC, and FPGA design. Designers can use SpeedCHART to capture their specifications with a variety of graphical editors (FSM, schematic/block, truth table, etc.) verify these specifications in an intuitive simulation/animation debugging environment, and then translate the graphics into simulatable and synthesizable Verilog or VHDL. Direct-Drive simulation is a feature for performing simulation of a SpeedCHART graphical specification using an external HDL simulator. The simulators supported by Direct-Drive are Verilog-XL, Simline, VCS, and Leapfrog. SpeedCHART v.3.1 costs $16,500. Options such as Direct-Drive start at $3,500. Speed Electronic, Santa Clara, CA Contact Jim Stewart: (408) 980-0884.

Front-end tool ICAP/4Lite Xtra includes all the features of ICAP/4Lite and adds a full-featured graphical waveform post processor and model libraries with over 6,000 parts. It also provides an integrated schematic entry front-end and a version of the IsSpice4 simulator with unlimited circuit size. ICAP/4Lite Xtra includes over 6,000 Spice models; 4,600 analog parts, 175 digital parts, and over 1,300 vendor-supplied IC/op-amp models. List price for a single copy is $995. ICAP/4Lite Xtra owners can update their software to the full ICAP/4Windows product for the price difference. Intusoft, San Pedro, CA Contact Charles Hymowitz: (310) 833-0710.

FPGA Actel's 3200DX, a new family of high-capacity FPGAs, reputedly combine the best features of FPGAs, CPLDs, and dual-ported SRAM in one device. The 3200DX family is the first of the Integrator FPGA series. It will offer 40k gates and 3.5 kbytes of dual-port SRAM. The family is supported by a wide range of design automation tools. It is based on Actel's antifuse architecture and delivers flexibility and efficiency for designers using synthesis or schematic entry. The dual-port SRAM banks offer 5ns synchronous access times. The SRAM is arranged in 256-bit blocks configurable as 32 x 8 or 64 x 4 with separate clocking for read and write ports to implement true dual-port access. The initial member of the 3200DX family is the 6.5-kgate A3265DX. It is packaged in an 84-pin PLCC, and sells for $72.50 at introduction for 500 pieces. In 1996, volume pricing is expected to be $29.50. It will also be available in a 160-pin PQFP and a 176-pin TQFP. Actel, Sunnyvale, CA Contact Tom Todd: (408) 739-1010.

Parasitic extraction point tool MaskPE Station is a stand-alone tool with distributed computing capabilities for full-chip parasitic extraction offering capabilities approaching the level of accuracy previously found only through a 3-D field solver. It provides users with the ability to model critical 3-D effects with 2-D calculations, such as accounting for interconnect charge sharing between conductors on the same or different layers on all nets in a design. Parasitic extraction for all nets in a design allows designers to focus their efforts on solving the problems of true critical nets. Three key features in MaskPE Station are interconnect charge sharing relationships, user-defined equations, and the ability to "see" lower-level cell data while calculating parameters. MaskPE Station reads multiple formats directly, including all of Mentor's physical design formats, and outputs HSPICE, Lsim, and SDF delay files. It is available for installed platforms on Sun, Hewlett-Packard, and IBM workstations, and is priced at $68,000 for a node-locked license. Mentor Graphics , Wilsonville, OR. Contact Lillian Tsai: (503) 685-1177.

integrated system design  August 1995