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Managing IC Design Complexity

A structured modeling approach to designing ICs which combines designer expertise with text, graphics, and simulators may be the best of all options.

By Prem P. Jain, Ph.D.

As integrated circuits become ever more complex, designers search for better tools and methods to improve design quality and reduce design time. Some use graphics, some use text, and most use simulators. Though we like most things in these approaches, each alternative has its limitations. In fact, the best solution for complex design capture and validation may be a structured modeling approach combining designer expertise with the best capabilities of all three: graphics, text, and simulators.

This methodology, inspired by software/hardware architecture modeling techniques, proves to be exceptionally effective for functional and RTL designs of complex ICs. It utilizes graphics for design capture and validation, yet it captures only the concurrent behavior graphically. Sequential behavior is captured textually. The use of this approach eases model management and the evolution and validation of system behavior.

In the early '80s, designs were first captured graphically by schematics, later textually using HDLs. Recently, graphical HDLs have sweetened the languages, supplying them with what I call "syntactic sugar," for capturing designs visually.

Schematic and HDL-based design methods approach design validation and use graphical capabilities differently. Users of schematic capture describe their designs graphically and gain confidence in their work by eyeing the resulting schematics. In contrast, text-based designers depend primarily on simulation results and use graphics for design validation.

HDLs, which add concurrency and timing constructs to textual programming languages like C to represent hardware, incorrectly assume similarities in hardware and software systems. In fact, the two behave quite differently. Contrasted against each other, software behavior has much less concurrency and much greater complexity of sequential operations, while hardware behavior has more concurrency and less sequentiality.

Concurrency in hardware behavior takes the form of multiple pipeline stages, state machines, and executions of hardware instances in the same clock cycle. In general, hardware behavior needs to capture sequential and concurrent operations, along with time, for each of these operations. For these reasons, hardware behavior capture requires both graphics and text. Alternatively, with few exceptions, software behavior can be described textually.

Using text to represent sequential behavior and graphics to capture concurrency reduces the model size in terms of textual pages and graphs. Designers validate each sequential code independently through program debugging environments, then organize these sequential codes and debug system-level designs using the implicit hierarchical and visualization capabilities of graphical capture.

By employing a structured methodology combining the expertise of the designers with the best capabilities of graphics, text, and simulators, developers gain an additional opportunity to optimize their designs by exploiting natural concurrency in the design specifications and creative component sharing in the implementation of the operations. In addition, they may significantly improve the quality and the quantity of communications--necessary for complex designs--among project team members.

Prem Jain is president of C.A.E. Plus, Inc. He led the research in architectural synthesis at the University of Texas at Austin.
integrated system design  March 1995

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