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A New Dawning in EDA High-level design automation may be the next wave in the industry, but what hurdles must be overcome? Dr. K. Larry Lai

Most electronic design automation (EDA) start-ups manage to establish themselves in the marketplace despite the presence of relatively large and well-financed EDA vendors such as Mentor Graphics (Wilsonville, OR) and Cadence Design Systems (San Jose, CA).

Start-ups have been responsible for the bulk of technical innovations in the industry. Why? Because the EDA market continually undergoes fundamental shifts that fast-moving start-ups are best positioned to exploit. One of the shifts currently under way is in design methodology.

Design methodology has been shifting from schematic-based computer-aided engineering (CAE) to high-level design automation (HLDA), utilizing hardware description languages (HDLs) and logic synthesis. HLDA is fast becoming the design methodology of choice because it automates the logic design process, thereby shortening significantly the design cycle.

While HLDA has been growing much faster than other segments of EDA, less than 20 percent of the electronic designers in the United States have adopted HLDA to date. In Japan, it is less than 10 percent. The main barrier to adoption lies in steep learning curves necessitated by complex HDL syntax/semantics, and synthesis tools that are hard to learn and master. Many companies simply cannot afford the cost and delayed time to market of retraining all of their hardware designers and risk turning them into mediocre HDL programmers.

Even though HDL-based design methodologies have been around for more than 20 years, the vast majority of hardware designers still prefer to think in terms of block diagrams, state diagrams, Boolean equations and timing diagrams. To completely describe a design, they must capture not only functionality, but also functional test vectors, library elements and timing constraints.

Many designers tell us what they need is a graphical environment that is easy-to-use and can capture full design intent using design paradigms with which they are already familiar. They also want the environment to hide artificial complexities brought on by intricate languages and non-intuitive tool interfaces.

Time-to-market has become such a key competitive factor in the electronics industry that meeting functional and performance requirements in the shortest possible time is often the number one priority. The key to minimizing time-to-market lies in the support of design reuse and performance-oriented implementation.

Design reuse, like object-oriented programming in software development, is the most effective methodology for rapid development of electronic products. Performance-oriented implementation, on the other hand, complements design reuse by maximizing cost performance within given technology and cost constraints.

The EDA industry must respond to the needs of electronic designers who have to adopt HLDA to remain competitive, while at the same time, cannot afford to spend months learning through trial and error how to use HDL and synthesis tools. Given an easy-to-use graphical environment, many designers would rather treat HDL as an intermediate language than as a language to describe their designs in.

To the 80 percent of electronic designers who have not yet adopted HLDA, the shift in design methodology is just beginning.

Larry Lai is president and co-founder of Escalade (Sunnyvale, CA). He previously led the development of Design Framework at Cadence Design System (San Jose, CA) and was the creator of SKILL, Cadence's extension language. He holds a Ph.D. in computer science from Carnegie-Mellon University in Pittsburgh, Penn.

integrated system design June 1995