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IC Signal Crafting: the Key to Successful Interconnect Design As higher speeds and greater design complexity cause previously ignored problems to threaten signal integrity, chip designers must adopt new methodologies. by John Cooper

Until recently, interconnect routing was not a critical concern of IC designers. Increasingly higher operating speeds, however, are bringing interconnect-related problems to the forefront; especially when implemented in deep submicron process technologies. While simple linear timing models (e.g. distributed RC delay models) once provided sufficient placement solutions, they become inaccurate at higher speeds. Higher speeds and greater design complexity are also causing problems of signal reflection, interconnect delay, and crosstalk. Previously ignored factors now threaten to degrade signal integrity, or the ability to preserve the original signal waveform.

What all of this means is that chip designers must begin adopting new design methods, some of which have their origins in high-speed printed circuit board design. The term we at Cooper & Chyan Technology have adopted to describe this new technique is "signal crafting." By this, we mean an IC design methodology that achieves timing and noise specifications by accounting for interconnect behavior throughout the design process. Toward that end, we believe timing-driven and noise-controlled routing are fundamental capabilities required to "craft" the interconnect so that timing, electrical, and physical design goals are achieved.

New advances in front-end design methodologies have given powerful synthesis and timing analysis tools that provide the timing constraint information required to drive timing-sensitive layout systems. To date, the linking of logic synthesis with floorplanning and placement has provided a means to limit pre-layout errors due to interconnect delay, but this approach does not satisfy timing and noise requirements.

What engineers require is a router that understands several timing requirements and can adjust net topologies to meet those requirements. It must understand electrical property differences between layers and vias. It must be able to repair surrounding wire topologies to bring all paths into compliance without introducing new violations. Perhaps one of its most critical functions, the router must also be able to control parallelism so as to effectively control crosstalk.

Crosstalk is perhaps the least understood factor affecting signal integrity, and the most difficult to detect and manage. Its impact on circuit performance, however, has become a first-order effect that must be managed as part of any timing-driven routing solution. Crosstalk is the unintended interaction of one circuit with another, mainly due to capacitive and inductive coupling effects of interconnects. This coupling degrades performance by imposing additional interconnect delay and by distorting signal purity to produce false logic highs and lows.

Once crosstalk is detected in certain nets of a design, the challenge is to remove the cause. We believe the solution is noise-controlled routing, which intelligently manages interconnect behavior to reduce or eliminate crosstalk, and employs special wire topologies. For example, the router must be able to separate nets that are producing crosstalk in adjacent interconnect.

Just as tools that link layout to synthesis improve the accuracy of pre-layout interconnect delay, a link between physical layout and analysis tools will ensure the signal integrity of analog, high-speed, and deep submicron designs. Signal crafting methodologies will mature as these links between routing and analysis tools as well as the links between routing tools and synthesis/floorplanning/placement improve.

John Cooper is co-founder and chief technical officer of Cooper & Chyan Technology (Cupertino, CA).

integtrated system design  July 1995