ASIC Issues

More Clocks in Less Time High complexity, deep submicron, and the resurgence of hardware acceleration for design verification. by R.T. "Tets" Maniwa

The recent announcement by Mentor Graphics Corp. (Wilsonville, OR) to purchase Meta Systems (Saclay, France) for their hardware emulation systems technology and product line indicates a tacit admission that the software simulators are reaching their limits. The alternatives available to the designers to bolster simulations are increasing and seem to indicate a trend away from more simulator seats towards hardware acceleration.

Speed is the main problem in simulating very large designs. The number of clock cycles needed to simulate system operation can exceed millions. The simulation needs to run a set of applications, but it also needs many hours to simulate a small number of processor clock cycles. Most simulators work in the range of one to ten simulated clocks per second. Booting Windows on a 100MHz Pentium takes over a minute (six billion cycles). A workstation-based simulation of the Windows boot process would take over 19 years at the ten cycles per second pace.

The paradigm of faster simulations based on faster workstations is reaching its limits. Workstation clocks are already in the hundreds of megahertz and can, at best, double every two years. The foreseeable performance improvements certainly are not the orders of magnitude increase that designers need for the large designs. Additional simulator seats and parallel processing helps the situation, but they only provide linear improvements at a fairly high incremental cost.

One software-based alternative is to change to cycle-based simulation. Cycle-based simulators speed up simulations by changing the basic algorithms. These simulators require synchronous design styles and have less timing accuracy. They only calculate states on the clock edges (unlike event driven simulators). They achieve higher through-put, in the hundreds of cycles per second, as a result of the reduced computational loads. The cycle-based simulators help in getting more clocks per second, but the required design style changes and the lack of accuracy may limit the techniques to only those areas where the outputs can tolerate the trade-offs of speed for accuracy.

One way to improve simulation and verification through-put is to move more of the process into hardware. In the same manner that a logic function is accelerated by moving it from software to hardware, the simulation is accelerated by moving from software to hardware. Time-to-market and increased engineering design requirements are driving more people to consider the various hardware accelerators--logic accelerators, logic emulators, or system emulators--as a part of their ASIC design methodology. The hardware-based solutions offer large increases in simulated cycles per second. Logic accelerators can simulate a few thousand clocks per second while emulators exceed 1MHz at a cost of a few extra simulator seats.

At the low end of the performance range are the hardware accelerators. These systems are mixtures of dedicated hardware and software that speed up the gate-level simulations by factors from 10x to over 1000x the base software. The products from IKOS (Cupertino, CA) and Zycad (Fremont, CA) provide all the debug and trace capabilities of the software simulators at one hundred times the through-put of the software. Although the simulators are not fast enough to perform hardware-software co-design, the system performance is more than sufficient to run the application code segments that exercise the hardware-software interfaces. In addition, since these systems are simulator based, none of the timing, X-state, or Z-state faults cause problems or are missed as they might be in an emulator. The simulator type environment also gives full node visibility to facilitate the debug process.

After the simulations are more than 80 percent complete and correct, the use of a logic emulator increases clock speed. The design group can start the verification process by loading the design into a logic emulator. Hardware emulation systems perform at clock speeds exceeding 100KHz (going up to tens of megahertz). These dedicated systems include facilities for logic tracking and signal insertion at the gate level. The hardware systems emulate the design by partitioning the logic into smaller blocks that are programmed into the hardware.

In addition to the design groups, other people are looking at emulation as an important part of the approval process. Besides their own verification at the design level, some of the ASIC vendors are starting to look at emulation as a design sign-off requirement. They cannot afford the weeks of simulation time for sign-off on a large design, but they need to know the part will run in the system. They gain great leverage in getting the silicon to production if the silicon represents a known-good product--demonstrated by running it in an emulator. A design spin costs the ASIC vendor up to three months of production volume, valuable time in a billion-dollar facility. Time-to-market and fab loading preclude multiple silicon spins because the ASIC vendors need to work on getting the designs to production. ASIC vendors are hoping emulation will improve the number of design starts going to production (currently about half) and keep the wafers moving in fab.

High-speed applications, such as multimedia and networks, make emulators a necessary part of the verification and prototyping cycle. These applications require I/O in human response times and consume millions of clocks to process the data. In addition, the software needs to work seamlessly with the hardware. The requirements for high speed and hardware-software co-debug preclude all non-hardware solutions.

A few caveats are in order. Emulators can help solve many problems with speed issues, but they can spawn others in execution. One problem is the requirement to get the bug fix rate into the low single digits or, conversely, to get greater than 80 percent of the design verified before starting to load the emulator. Before porting the design to the emulator, an accelerated simulation helps gets the code verified. Otherwise, a major part of the design effort will go towards debugging bad code in the emulator. Although companies consider the emulators too expensive and too difficult to use, the emulator vendors are addressing the ease-of-use and cost issues. Finally, users need to plan for the large staffing requirements to load the design into the emulator. The emulator vendors offer consulting services to help with the implementation phases.

Quickturn Design Systems (Mountain View, CA) is the market leader in this segment. Quickturn's architecture is based on partitioning the design into a large number of small blocks that are implemented in a sea-of-FPGAs. The high-performance systems permit ASIC operations with system clocks up to 5MHz. The emulator permits an earlier start of system integration by enabling hardware co-design and verification. Although the emulators do not operate at full speed, the timing relationships are kept correct by partitioning and by the compilers, placers, and routers for the programmable elements in the system.

Quickturn recently signed an agreement with IBM for access to verification tools that IBM has been developing for high-speed computers. This agreement gives Quickturn exclusive rights to technologies for high-speed emulation and verification. It will also give Quickturn new capabilities in high-speed emulation.

The Virtual Machine Works (Cambridge, MA) system also uses a sea-of-FPGAs, but it addresses the I/O versus internal logic density in an FPGA by multiplexing I/O lines to internal logic blocks. They claim that their architecture and software can handle all types of clocking schemes because of their virtual wire concept and a compiler that automatically reconfigures logic to produce timing correct implementation in the FPGAs.

Meta Systems, now a part of Mentor Graphics , has a full-custom programmable device that addresses the logic and interconnect issues by including some of the interconnection resources on-chip. Mentor -Meta Systems has positioned the SimExpress Emulator as a hardware-software co-design tool. The software tools assist in earlier emulation in the design process, as early as the RT level.

The former Arkos, now a part of the Logic Modeling Group of Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys (Mountain View, CA), is also working on a full-custom device to do logic emulation. The Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys emulation and verification solution will address a higher level of abstraction and will support both hardware and software models in a time-slice architecture. They anticipate reduced time-to-emulation, improved debug productivity through better internal node visibility, and the look and feel of the standard debug tools.

The Aptix system and the Zycad Paradigm RP operate at a higher level in the system and can even include a logic emulator as one of its components. These modular system-level machines support complex hardware blocks like processor cores and memories through add-in components or daughter-boards. The systems can mix the capabilities of the random logic emulation with the actual performance of the large functional blocks.

For the ultimate in speed, nothing beats a gate-array device. Obviously, simulations must be more than 95 percent verified to be useful, so again, the logic accelerator may be the proper design medium. A pass on a quick wafer prototype service is less expensive than most other hardware alternatives but requires very high levels of confidence to offset the relative risks. The silicon can be turned very rapidly, but the costs add up very fast for incomplete or incorrect designs. Chip Express (Santa Clara, CA) can program a gate array with up to 100k gates in a single day. Other vendors like Orbit (Sunnyvale, CA) can turn a wafer in under a week.

There is no solution to the verification crisis except for careful engineering. Emulators, simulators, and accelerators all play a role to make careful engineering a possibility for a complex system design project. *

Tets Maniwa is a technical editor for Integrated System Design

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  March 1996