Is a System-on-a-Chip a Good Idea? The drivers for ever-higher levels of integration may be running up against other limits. by R.T. "Tets" Maniwa

A number of ASIC companies, including NEC Corp. (Mountain View, CA), IBM Corp. (Armonk, NY), LSI Logic Corp. (Milpitas, CA), and Toshiba Corp. (New York, NY), have announced multi-Mgate ASICs with the potential for a complete system-on-a-chip. These system-level ICs can hold a processor, customized datapath for special data processing, and some of the system RAM and ROM on less than one square inch of silicon. The availability of cores and libraries of functional blocks means that the designer does not have to design the million gates of circuitry, but only the 40 to 100 kgates of random interconnect.

The changes in silicon processing technologies permit more functions to exist in the same space as the previous generation of processes. Twice as much performance (speed and logic-density) may cost less in a 0.35-µm process than the equivalent in a 0.6-µm process. The system-level IC will have fewer I/Os than the combined chips since many of the signals will be on-chip rather than going from chip-to-chip. This reduces pin count and power consumption in the single chip IC.

Even though the ASIC vendors can make a multi-Mgate array and are encouraging users to put everything for a system on a single chip, the need of many people to use the very large arrays is fairly small. For those people who absolutely need the performance and level of integration at any cost, the large chips are essential for implementing the next-generation machine. Size, power, and system packaging considerations will drive the decision towards a single-chip solution.

In spite of the higher discrete costs for the system-level IC, it can still be a cost effective implementation if you count all the system costs. The extra costs for a chip set include many hidden costs such as matching requirements for the proper device mix and the extra costs of ordering and inventorying the various parts. The chip set may require binning or, in the extreme, may have to be part of a matched set, which will further exacerbate inventory and planning problems. Ask Apple Computer (Cupertino, CA) about optimizing the parts count. In addition, the single-chip solution permits the optimization of pin-outs and internal datapaths for specific functions and ameliorates the chip-to-board-to-chip interface problems.

For the rest of the world, the issues are not that simple. As gate counts increase, other characteristics also tend to increase. The maximum die size will not change much, since the maximum reticule size is the limiting factor. Power consumption, however, increases as a function of the total number of clocked gates and the increase in operating frequency (Power = µW/MHz/gate). The decrease in supply voltage (Power × (V2)) may compensate for some of this power. Pin count increases at approximately the square root of the gate count, and the advanced packages can cost over $0.10 per pin. Up to half of the pins have to be dedicated to power and ground, and the trend for wider bus sizes exacerbates the problem.

Consumers are very intolerant of dead-on-arrival hardware, so the testing must become exhaustive and extensive. The testing represents about 30 percent of the cost of an IC. Complete test coverage for an Mgate device is much more complex than for a set of smaller devices, even with scan and IDDQ techniques to reduce the number of test vectors. The suite of test vectors for a large device exceeds the capacity of the tester RAM. Test development can take as much time as the IC design and can delay the whole project, since the test development rarely finishes until after the ASIC design is cast in GDS-II.

Figure 1. The graph shows the estimated cost for various gate counts for 0.5-µm and 0.35-µm processes.

The higher level of integration reduces internal node visibility and forces a pins-out view of device operation. Along with the increase in design and debug difficulties on the hardware side, the large chips present greater challenges in hardware-software integration. How would you plug an ICE based on a standard processor into a portion of an ASIC? How would you access and bring up the operating kernel of a system buried within an ASIC? A logic analyzer is channel and memory depth limited for the number of signals in use. If the designer didn't anticipate the debug and software integration requirements in the early parts of the design, the tasks of system integration may take longer than the design.

The primary consideration for partitioning the system into multiple chips is the cost. The literature suggests costs are a function of chip area and complexity. A larger chip costs more than a smaller chip of the same complexity. A higher complexity chip will be more expensive due to the internal development time and because the vendor's verification time, as reflected in the NRE, will be much higher. In addition, the lower yield at electrical test and more expensive testing increases the on-going costs. The ASIC vendor plans to get revenues of about $8k for each wafer processed, so the price is an inverse function of the yield. Figure 1 shows the expected costs versus the number of gates.

The larger logic content will require higher pin counts and more expensive packages due to the increased pin count and heat dissipation capacity. The package costs on both a per-pin and total pin-count basis will increase. A 204-lead QFP costs about $0.02 per pin or about $4.00. A 256-lead BGA costs about $0.10 per pin, although this is projected to go down as BGA volumes increase, for a total package cost of $25.00. The 1000-pin CBGA is projected to cost up to $0.15 per pin, resulting in a $150.00 price for packaging and assembly. Finally, the high-density packages require a more expensive and complex PC board to handle the higher density of interconnects (8- to 20-layer vs. 4-layer).

The case for multiple chips versus a single chip is a function of a number of factors. Not only are the die yields and associated costs worse for the large chips, but the very large designs will have much longer simulation and synthesis times than the sum of the many smaller circuits. The time for verification and test development is now greater than the design time. Newer tools, software bus-level models, and still more changes in the design flow will help on the design and simulation ends, but the verification and implementation challenges will only get worse.

The multiple-chip approach gives the ability to repair or upgrade systems as technologies and system requirements change. The smaller chips have a smaller percentage of their pins dedicated for power and ground, helping to reduce the total package price. The quantity of parts helps with the distribution of heat sources compared to a single chip and lowers PCB interconnect density. If the cost of a set of parts is comparable to the cost of the single chip, the rest of the system-level implementation should determine the technology choice.

Beyond the cost issues, some of the workstation manufacturers state that one of the problems of a system-on-a-chip is the product differentiation. If the hardware is the same for all platforms, then people will figure how to get the full performance of the top-end machines from a lower-grade machine and will inform the rest of the world through an Internet posting. In addition, the lower-grade machines will have extra unused hardware, implying higher costs for power supplies and cooling equipment.

Ten years ago, when 50 kgates constituted a very large design, the goal in high-level integration was to put a system on a whole wafer. Now processing technologies permit a million gates and a megabyte of RAM on less than a square inch of silicon. Then and now, the greatest difficulty is making a cost-effective single-chip solution. The system on a single chip enables more features in a smaller space than previous implementations. The "super chip," however, may not meet the cost and time-to-market goals so critical in today's markets.

Tets Maniwa is a technical editor for Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  June 1996