DAC Special Section

The State of the Art in IC Layout Migration

Multiple processes for a design require the ability to migrate the design from process to process.

by Jonah McLeod

Designers working in fabless semiconductor companies or large system houses have traditionally generated their own layouts using customer-owned tooling for their application-specific standard products (ASSPs). By contrast, ASIC designers who provide netlists to ASIC vendors have largely ignored layout considerations. In deep submicron process regimes, interconnect contributes far more to circuit delay than do gates, thus requiring ASIC designers to perform placement of circuit components. To cut iterations between ASIC vendor layout and netlist design, system designers have begun to layout their own netlists just like ASSP designers.

Designers who have their own layout tools face the burden of maintaining a number of different libraries--one for each process at every foundry. Each library can comprise several hundred standard cells. Therefore, librarians in companies that do their own layouts value a tool that can automatically migrate a cell library quickly and accurately from one process technology to another.

For system designers who buy their own layout tools, one solution is to eliminate the library maintenance problem by purchasing third-party libraries. Georg Janac, chief technology officer at High Level Design Systems Inc. (Santa Clara, CA), says "system designers buy libraries for the standard cells needed to create unique designs." Furthermore, third-party standard-cell libraries provide immediate access to more than one foundry. These designers differentiate their circuits by creating custom datapaths and state machines.

One other part of this new design paradigm is commercially available cores--controllers for PCI, MPEG, etc.--that are more cost effective to buy than to build. Creating cores that can be easily transported from one process to another is the key, explains David Evans, strategic marketing vice-president at Technical Data Freeway (San Diego, CA)--a vendor providing VHDL and Verilog netlist models.

Library companies are promoting solutions that allow designers to fab circuits at a variety of different foundries. TDF provides synthesizable cores that are timing correct for a given process technology. By contrast, standard-cell library companies provide models with GDSII layout for a given process.

Libraries offering high-density layout Last March, Compass Design Automation Inc. (San Jose, CA) debuted its Optimum Silicon (OS) library. According to Albert Stritter, product-line manager of library and tool development, the new library afforded 20 to 40 percent higher density without giving up speed. Compass creates libraries that obey a common set of design rules that different fabs can produce. A designer building his circuit with the Compass library is assured that he can build his design on any of these fabs.

Writing in the February edition of Fabless Forum--the newsletter of the Fabless Semiconductor Associations (Dallas, TX)--earlier this year, Ken Brock, library marketing manager at Compass, claimed the Compass approach yielded silicon results that were only 3 to 5 percent less efficient than foundry-specific libraries.

Compass argues that foundries are largely buying the same process equipment from the same vendors; thus, the variation in process from one foundry to another can easily be comprehended by a common rules-set. Denise Slocombe, product marketing manager at Cascade Design Automation (Bellevue, WA), takes exception to the claim. The 0.5-µm processes of a foundry in Taiwan compared to a foundry in Japan, Korea, or the U.S. are optimized for different results; thus, one library cannot fit all.

Migration tools--a user perspective

MOSAID Technologies Inc. (Kanata, Ontario, Canada) designs advanced chips for standard and application-specific memory (ASM) requirements and designs, manufactures, and distributes engineering test systems for memory chips. As a company that provides design services, we need to deliver our product as quickly as possible while maintaining a high standard of quality. After 21 years of experience, MOSAID has designed many ICs in various processes. To accommodate many kinds of DRAM and ASIC processes, we had to find a solution for the migration (conversion) of a layout from process to process.

Based on our needs, we considered various methodologies capable of efficiently retargeting layout between various processes. There are 2 different ideas about layout conversion: (1) to generate layout inside tools that can retarget the results based on different design rules, and (2) to migrate GDSII or CIF libraries from one process to another. Each of these methodologies has advantages and disadvantages. In both methodologies, once the generation or migration technology file is written for one process, the second process migration will be very fast, assuming an evolution and not a revolution of the processes. Layout migration is not appropriate in the case where there are drastic differences between the source and target process--for example, 2 layers of metal to 3 layers of metal.

Type 1--generating a new layout


* You have to generate everything inside the tool. 
* You have to become an expert not only in laying out the cells but in 
understanding the specific tool philosophy. You also need a more detailed 
software background to write generators.
* The result is never perfect in either methodology,
but in this case you have 
to work within the tool to get the desired results. In general, the 
generators do not have a full-polygon pushing editor attached to the tool. 
If so, the tool is quite primitive. You need many iterations until the result 
is acceptable, especially if your target is a library that is to be used by a 
specific tool--for example, Cell3 Ensemble, from Cadence Design Systems 
Inc. (San Jose, CA), Arc Cell, from 
Avant! Corp.
 (Sunnyvale, CA) , and Sonic, 
from Silicon Valley Research Inc. (Mountain View, CA), etc. 
* Once out of the system you cannot backannotate subsequent improvements 
to the source. 
* It cannot be used to migrate old libraries or chips that were not previously 
developed with this methodology. 
* You can change cells/blocks topologies inside the tool. 

Type 2--migrating the GDSII or CIF


* You can generate the libraries with
any kind of Layout editor, or you can 
use the old ones. 
* You don't have to be a layout expert to use the converter if the cells/blocks 
are designed by somebody else: these tools use standard formats as input 
-for example, GDSII or CIF. 
* If the result of the conversion is not satisfactory, you can use a normal 
layout editor to change the source and rerun the tool. 
* You cannot change the cell topology to take advantage of different process 
limitations/advantages: the source topology is
maintained. 
* You need to own a separate layout editor to be able to modify the source.

Many layout conversion tools were initially developed in university labs. Some of them have become commercial products; others are still available only to university students. For example, Simon Fraser University (Burnaby BC, Canada) has developed a C Design Language (CDL) that is a synthesizer. It can accommodate contact cells, has module generator support, place and route tool retargeting capabilities, and easy process retargeting capabilities

The following is a list of tools that can be used for process-independent layout cells and/or layout converters.

Library Layout-Standard Cell (LILA-SC) A type-1 product from Cadabra Design Technology Inc. (Nepean, Ontario, Canada), LILA-SC is a standard-cell synthesizer containing automatic programs for placement, routing, and compaction, complemented with an interactive editing tool. This tool can port a standard-cell library from one process to another by simply plugging in a different rules file. The only small drawback is that you have to generate the cells inside the tool.

Device Layout Editor (DLE) A type-1 product from Cadence Design Systems Inc. (San Jose, CA), DLE is a schematic-driven layout tool with predefined symbolic transistors. The various kinds of straight, bent, or folded transistors can be defined in a basic symbolic library that the tool uses to change size. After place and route the tool has a compactor. The advantage to this approach is that topology can be changed if the libraries are residing in the system. If a GDSII file was generated for tapeout, the GDSII cannot be input back into the DLE. After writing a new rules file and preparing some transistors, you can immediately generate a new library. Pricing starts at $12k.

Layout Automatic Synthesizer (LAS) Another type-1 product from Cadence Design Systems Inc. (San Jose, CA), LAS is a synthesizer that uses as inputs a rules file, schematic, or netlist and outputs a DRC- and LVS-correct layout. The result is not optimal but it provides a push-button solution once a new rule file is written. The number of transistors should not exceed 12 kgates. Pricing starts at $50k.

MasterPort A type-2 product from Cascade Design Automation Inc. (Bellevue, WA), MasterPort reads a GDSII layout, and derives the important information related to topology. With the new design rules, it can generate a new cell. The only limit is the size of the leaf-cell it handles--up to several hundred transistors. MasterPort sells for $150k.

Compiler Development System (CDSII) A type-1 product from Cascade Design Automation Inc. (Bellevue, WA), CDSII is a library development tool that includes a device compiler. The generator is written in C. Constraints can be added graphically or in text to the C code. This generator outputs GDSII, SPICE, and delay information. The systems sells for $225k.

Rockwell Symbolic Editor (ROSE) A type-1 product from Compass Design Automation Inc. (San Jose, CA), ROSE is a tool originally written by Rockwell. ROSE is a symbolic/parameterized/polygon tool based on the concept of a special GRID for each layer. If an entire chip is designed inside ROSE, the database can be migrated DRC- and LVS-correct by changing the necessary rules. The disadvantage is that the tool does not have a real compactor, so non-linear design rule changes prohibit taking full advantage of some design rule enhancements.

Library Synthesizer A type-1 product from Excellent Design Inc. (Santa Clara, CA), Library Synthesizer features a process independent object-oriented standard-cell compiler and an automatic library synthesizer. The compiler generates C-language based GDSII layout objects. Their library is optimized for Cell3 routing.

Schematic Driven Layout (SDL) A type-1 product from Mentor Graphics Corp. (Wilsonville, OR), SDL is a group of transistor generators and compactors that use process definition files and schematic or netlist as input. You can quickly generate DRC & LVS correct layouts, and the layout is reusable in ICstation format. In migrating layouts, the tool will regenerate the transistors using new design rules and run ICcompact for DRC correct results. The newest feature is ECO capability. The product sells for $34.9k.

ICgen Another type-1 product from Mentor Graphics Corp. (Wilsonville, OR), ICgen combines all the features related to process information and migration from GDT, CAECO, and ICgraph to help generate a process-independent library. A big advantage based on GDT database is the automatic extraction of the layout for simulation purposes. Pricing starts at $55k.

Layout Conversion Environment (LACE) A type-2 product from RubiCAD Corp. (San Jose, CA), LACE needs a GDSII file, a design rules file and a few constraints to generate a new DRC correct GDSII file for new process requirements. LACE can handle many kinds of design styles with non-orthogonal structures and many types of devices. LACE accelerates DRC technology conversion of existing IC mask layouts. It is a hierarchical tool and can convert big blocks or full library cells at once. The tool has a very good mask layout conversion capability able to handle a wide range of requirements. LACE sells for $250k.

Design Rule Enforcer and Manager (DREAM) Another type-2 product from Segantec Corp. (Milpitas, CA), DREAM is a tool for rapid retargeting of cells, blocks, or chips from one process to another. The tool requires a source GDSII or CIF file and new process file to generate new DRC clean GDSII or CIF file. The tool handles hierarchy, recontacting, and 45 degree compaction. The TILER is used to maintain all the constraints, connectivity and placements in place when DREAM converts a library or a block with touching cell boundaries. An easy user interface allows the user to see and modify some topology to take advantage of new process features. The MIGRATE interface addresses any process, methodologies or requirements. MOSAID owns a copy of DREAM. We have used it on a few occasions and it has saved us time migrating from process to process. The tool sells for $125k for a full featured version; a lite version retails for $75k.

Dan Clein is the manager of IC layout at the Semiconductor Division of MOSAID Technologies Inc., (Kanata, Ontario, Canada).

QuickPort--layout-level design portability

QuickPort is a layout-level porting software developed by Aspec Technology Inc. (Sunnyvale, CA). To understand how QuickPort works, you must also understand the underlying architecture--Aspec's HD (high density) Architecture.

The HD Architecture is a strict grid-based architecture. Both the cell layout and chip layout interconnects follow the same grid system. Furthermore, from process to process, all macrocells have the same I/O pin locations, even though the internal layout may be different to accommodate the design rule differences.

Using the HD Architectures, the chip layout for a given design is simply a 2-D array of grids. QuickPort preserves the relative placement and routing of all cells, performing a non-linear transformation of the grid spaces to the target process and inserting the target process' macrocells. As a result, the final layout is as dense as the target process allows and is functionally correct.

QuickPort is a safer approach than process compaction and Common Design Rule (CDR) because the new layout database can be read into the place and route software for timing backannotation and engineering change orders. Timing backannotation is important because it insures that the designer can verify that the design is timing-correct and that it meets the performance requirements. The QuickPort process takes less than one hour for a 100-kgate design. Including timing verification, the entire porting process can be completed in two weeks.

Process migration follows the same methodology, so QuickPort is as applicable for targeting new processes as it is for second sourcing.

QuickPort limitations First, the design has to be based upon the HD Architecture. Secondly, the current QuickPort technology requires that the source process and the target process have the same number of metal layers. Therefore, QuickPort may not produce the densest die size for some designs that move from double-layer metal (DLM) to triple-layer metal (TLM) processes. However, it seems that most designs have already made these transitions, since 0.6-µm processes are generally based on TLM.

Regardless of the approach, increasingly ASSP/ASIC companies, whether fabless or fabbed, are adopting portability as a key business strategy. This insurance policy provides them with global access to capacity, second source availability, and the latest process technology.

Charlie Cheng is the director of marketing at Aspec Technology Inc. (Sunnyvale, CA).

Table 1
CDR approach for design portability using Aspec's HD Architectures*
Design Rules Sample	Typical Process(µm)	Best Case(µm)	Worst Case(µm)	Deviation
Diffusion Spacing	0.90	0.65	1.00	35%
Poly-to-Diffusion Spacing	0.25	0.15	0.40	63%
Poly Spacing	0.60	0.56	0.80	30%
Poly Gate Length	0.50	0.42	0.60	30%
Contact Width	0.50	0.42	0.70	40%
Contact-to-Gate Spacing	0.40	0.35	0.60	42%
Diffusion Overlap Contact	0.25	0.20	0.50	60%
Poly Overlap Contact	0.30	0.20	0.50	60%
m1 Overlap Contact	0.25	0.20	0.42	52%
m1 Width	0.60	0.25	0.90	72%
m1 Spacing	0.60	0.25	0.70	64%
Via Width	0.60	0.42	0.70	40%
m1 Overlap Via	0.30	0.20	0.80	75%
m2 Overlap Via	0.30	0.20	0.60	67%
m2 Width	0.70	0.25	0.90	72%

* Data compiled from 20 different 0.5-µm processes

The benefit of buying third-party libraries has one significant drawback: cost. Each time the designer wants to migrate his current designs to smaller geometries--0.8 to 0.5 µm--he must purchase an entirely new library for the target process from his vendor. At over $100k per license, the cost is steep but well worth the price if the design cycle is shortened.

Compaction tools for library migration Several companies are now offering tools to solve the problem of library migration for companies that own and maintain their libraries (see Migration tools--a user's perspective). One new offering is QuickPort from Aspec Technology Inc. in Sunnyvale, CA (see QuickPort--layout-level design portability).

Migration tools fall into the category of conversion and compactor tools. Jason Chang, director of technology development at Cirrus Logic Inc. (Fremont, CA), says conversion tools convert layout from one process to another. A tool such as Dracula, from Cadence Design Systems (San Jose, CA), can do the conversion, but it needs added programming to do compaction.

By contrast, a compaction tool accepts an existing layout in the form of GDSII or SPICE netlist, then applies the design rules files for a new process. The compactor then shrinks the existing layout to a smaller geometry layout converting the layout in the process. In operation, the compactor shrinks the cell in the horizontal direction until a design rule is broken, then does the same for the vertical direction. Afterwards, it begins to apply additional algorithms to further reduce the cell-size. For example, MasterPort from Cascade contains a capability called automatic constraint generation that defines spatial relationships between points within a cell layout, in terms of variable design rules, says Cascade's Slocombe. The capability permits a layout containing non-stacked vias to be optimized for a process that allows stacked vias.

Criticisms leveled at compaction tools include their difficult user interface, slow execution speed, and limitation on the size of designs that can be handled. RubiCAD Corp. (San Jose, CA) has taken direct aim at each of these in the newest release of Layout Conversion Environment, LACE 2.1.

Version 2.1 can now accept designs with up to 70k transistors, says Michael Reinhardt, president and CEO of RubiCAD . Before, the tool topped out at 50k transistors. In addition, the company has boosted the tool's algorithm so it has a 30 percent faster run time.

The use of 45-degree routes for increased compaction is the latest trend in compaction tools. Most compaction tools now offer this capability. RubiCAD has taken this function one step further by using intelligently compacted transistors that include sections designed at a 45-degree angle.

However, one continuing limitation with compaction tools is their inability to take advantage of added capability in new processes. For example, many of the new deep submicron processes offer three, four, and five layers of metal as well as new polysilicide layers.

Philip McGee, vice-president of technology and business development at Sagantec (Milpitas, CA), says the company's Design Rule Enforcer and Manager (DREAM) tool has the ability to accommodate additions such as polysilicide. A silicide process has one contact hole in each source-drain contact region. Nonsilicide processes tend to have multiple contacts. Migrating a design from a non-silicide process into one with polysilicide requires converting the multiple contacts to a single contact.

Tools that resize transistors Compaction tools are not only useful for converting libraries, they are now being pressed into service to solve timing problems in deep submicron design. In process technologies of 0.5 µm and smaller, interconnect delay far exceeds gate delay in determining critical path timing.

In current design flows, a floorplanner accepts a synthesized netlist as input, creates a placement of circuit components, and extracts timing for distances between the components. Invariably, a number of the paths fail timing, and the backannotated timing is returned to simulation and synthesis to fix the timing.

Sagantec's McGee explains that a new tool from Epic Design Technology Inc. (Santa Clara, CA) called Amps will automatically extract the correct transistor sizes for the failing critical paths of a design. Compaction tools from Sagantec, Cascade , and RubiCAD can input the data from Amps and can automatically change the transistors to the correct size to meet timing.

However, Martin Lefebvre, president Cadabra Design Libraries (Nepean, Ontario, Canada), takes issue with this claim. With compaction tools, a designer may have to make manual changes to get the compacted layout to work, says Lefebvre. With Library Layout-Standard Cell (LILA-SC), the compacted layout works with no intervention required.

To illustrate the point, Lefebvre cites the example of an instance where Amps specifies transistors too big to be created by enlarging a single transistor. LILA-SC would implement the required transistor as two separate transistors and automatically wire them together. Compaction tools lack the ability to synthesize new layouts.

Another example is found in the process migration from 0.5-µm to 0.35-µm rules. Numerically, the new process geometry is 70 percent smaller than the original. However, IC vendors routinely squeeze the geometry to 50 percent of the original to achieve further cost reduction. Such shrinks reduce the amount of routing resources available. "Where before, you had 10 routing tracks; now, you may only have eight," says Lefebvre. "Compactors could not cope with this problem; whereas LILA-SC simply synthesizes new interconnect."

There is one drawback to the Cadabra tool, however. It requires a netlist input instead of a GDSII file. Compactors all work with the latter.

The advent of tools such as LILA-SC is pointing the direction to automatic process migration. Such tools provide library owners an expedient for automatically transferring standard cells as well as complex cores from one process to another. The advent of such tools will eventually change the nature of IC design by providing a medium of exchange for high-performance silicon designs.

Jonah McLeod is editor-in-chief of Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  June 1995