ASIC Technology

Fab and Silicon Performance

An evaluation of the performance variations across processes from different IC vendors.

by Jonah McLeod

With the advent of deep submicron process technologies, designers are taking on more responsibility for back-end layout--placement and routing--of their design. Designers who were previously content with providing netlists to ASIC vendors are now using place and route tools to produce GDSII files, which produce the mask sets needed to fabricate final silicon.

However, with this newfound independence, designers must evaluate a foundry to determine if it can provide the desired chip size and performance. A major factor influencing both chip size and performance is metal interconnect, especially in deep submicron processes (processes 0.5 µm or lower). In addition, designers must also consider the foundry's design and process rules.

How interconnect affects performance Interconnect delay is the curse of deep submicron designs. "Deep submicron processes offer smaller, faster transistors, but, unfortunately, a vast majority of the delay is associated with the interconnect and not the gates," says Roy McGuffin, vice president, product line group, Meta-Software (Campbell, CA).

Just how much delay resides in the interconnect? Bhadrik Dalal, director of marketing for foundry business development at Compass Design Automation Inc. (San Jose, CA), describes the breakdown as 10 percent intrinsic gate delay, 25 percent fanout (on average around 2.7 loads), while interconnect makes up the remaining 65 percent. "If a gate is driving a net that runs between blocks, interconnect delay can represent up to 90 percent of the total," he says.

Managing interconnect delay is largely the designer's responsibility. However, Yen Chang, vice president of engineering at Aspec Technology Inc. (Sunnyvale, CA), points out that cell libraries that are more porous can also shorten interconnect delay, allowing designers to route over a cell, rather than jogging around it.

In addition, the foundries are doing their part to minimize wiring delay. As submicron processes shrink, wire widths within the design must also get smaller. However, as these widths get smaller, the wire must maintain a sufficient area for current flow. Foundries have solved this width dilemma by increasing the height of wire.

To further reduce delays, foundries now offer more metal layers, George Kern, CEO of I-Cube Inc. (Santa Clara, CA), declares. With upwards of five metal layers, metal lines can be made thicker and spaced wider apart.

Delay is also reduced by the use of polysilicide instead of metal, for intracell routing, Kern says. To lower resistance in the source and drain junction, IC manufacturers silicidate it using metal such as titanium. The metal and silicon react chemically, forming silicide, which reduces source-drain resistance an order of magnitude.

Finally, many foundries are beginning to add copper, a much more conductive metal, to the aluminum interconnect, says Eric Peltzer, marketing analyst, metal business unit, Lam Research Corp. (Fremont, CA). Copper content can vary from as little as 0.5 percent up to 4 percent, he states. Copper is not widely used because it's harder to deposit than aluminum.

Peltzer sees copper increasingly being used in smaller geometry processes. Copper can be deposited effectively down to 0.1 µm, while depositing aluminum at these smaller geometries is more problematic, he explains.

Typically, three, four, and five layers of metal, silicidation, and copper wires are being implemented by giant IC companies such a IBM Microelectronics Inc. (Essex Junction, NY). However, Taiwan Semiconductor Manufacturing Company Ltd. (Hsin-Chu, Taiwan) plans to offer some of this capability within the next 12 to 18 months. Expect other foundries to do the same.

Table 1
Typical design rules for 0.5-µm CMOS transistors
Design Rules Sample	Typical Process (µm)	Best Case(µm)	Worst Case(µm)	Deviation
Cell Density
1 Diffusion Spacing	0.90	0.65	1.00	35%
2 Poly-to-Diffusion Spacing	0.25	0.15	0.40	63%
3 Poly Spacing	0.60	0.56	0.80	30%
4 Poly Gate Length	0.50	0.42	0.60	30%
5 Contact Width	0.50	0.42	0.70	40%
6 Contact-to-Gate Spacing	0.40	0.35	0.60	42%
7 Diffusion Overlap Contact	0.25	0.20	0.50	60%
8 Poly Overlap Contact	0.30	0.20	0.50	60%
Routing Density
9 m1 Overlap Contact	0.25	0.20	0.42	52%
10 m1 Width	0.60	0.25	0.90	72%
11 m1 Spacing	0.60	0.25	0.70	64%
12 Via Width	0.60	0.42	0.70	40%
13 m1 Overlap Via	0.30	0.20	0.80	75%
14 m2 Overlap Via	0.30	0.20	0.60	67%

Table 1. Contained in the table are the typical, best-, and worst-case design rules for 20 different foundries all offering 0.5-µm CMOS process technology. Each of the design rules are illustrated in Figure 1. Table courtesy of Aspec Technology Inc.

However, assuming similar minimum device geometries, there is a fairly wide variation in performance in nominally similar processes, says Meta-Software's McGuffin. To illustrate the variability contributed by design rules, consider the amount of variations that exists among foundries.

Table 1 shows a sample set of design rules. The table was constructed by Aspec Technology using the design rules from the 0.5-µm process for 20 different foundries. The best- and worse-case rules of various vendors vary widely.

The first 11 rules contribute the most to cell density, while rules 9 through 14 affect routing density of a design, Martin Scoones, explains process technology engineer at Cascade Design Automation Inc. (Bellevue, WA). Figure 1 shows how the design rules relate to transistor layout. Furthermore, among the rules, poly gate length contributes the most to transistor performance. Gate length controls performance because it determines drive current of a transistor, Scoones states. "In general, the smaller the gate length, the more drive you get."

Alex Sinar, director of manufacturing at Zoran Corp. (Santa Clara, CA), describes aspects of design rules that affect his company, a fabless semiconductor manufacturer. His company has long-term relationships with several foundries so that fab capacity can be expanded easily as demand increases. One concern for Zoran is ensuring that rules that work at one foundry, work equally well at another.

One rule of particular concern, for example, is metal pitches and metal overlap of contacts. Pitch refers to the width of a metal line and the spacing between the line and an adjacent wire (rules 10 and 11 in Table 1 and Figure 1). Metal overlap of contact (rule 9 in Table 1 and Figure 1) refers to the amount of metal overlapping a metal line where a contact exists on the line.

This spacing is critical in most of today's ICs because most contain wide buses running from one major block to another. Where one bus joins another bus or a logic device, Sinar asserts, there will be multiple contacts placed side by side in the layout. The spacing between the edge of one contact and the edge of its adjacent neighbor has to be consistent from one foundry to another, he explains.

How process rules affect performance While design rules affect performance and density, process rules have an equal, if not more profound affect. "We could come up with identical transistor size for two different foundries," says Aspec's Chang, but there could be differences in performance because of process difference.

Process rules refer to the electrical properties of a transistor produced by a given manufacturing process. Chang says electrical characteristics of saturation current and mobility of carriers in two different foundries' process can easily change performance by 15 percent. Spice models describe these characteristics for individual foundries.

The fundamental determinant of a transistor's performance is its beta. "Beta describes a transistor's current driving capability; the higher the beta, the more current drive," says Zoran's Sinar. This characteristic is dependent upon the "recipe" used to build a transistor.

In constructing a CMOS transistor (see Figure 2), the critical determinant of a transistor's beta is its chemistry and mechanical construction. A transistor is constructed in layers beginning with a substrate. The architecture of this structure determines the character of the device. Thus, a memory transistor has a different structure than a logic transistor.

In addition, a CMOS inverter consists of interconnected "n" and "p" field-effect transistors (FETs). To make nonconducting material conduct, dopants are added in the source and drain regions of each device ("p" diffusion and "n" diffusion in Figure 2). Typical dopants are phosphorous for "n" material, boron for "p" materials. The "recipe" a foundry uses directly affects the beta of transistors produced from that recipe.

Figure 1. The 2-input NAND gate is illustrated in silicon layout form. The silicon layout of the gate comprises a group of polygons layered on top of one another. The spacing of these polygons relative to one another is governed by the design rules contained in Table 1. The numbers in the left column of the table correspond to the numerical annotations in the silicon layout (note that #8 is not shown above). Annotations courtesy of Aspec Technology and Cascade Design Automation . Illustrations courtesy of Rubicad.

Another factor affecting transistor performance is gate oxide thickness: the thinner, the better (see Figure 2). Two poly contacts form the input to a CMOS cell. An input signal creates a field effect across a capacitor that is formed by the gate oxide between the poly contact and the diffusion regions of the "n" and "p" transistors. Thus, the thinner the oxide, the higher the capacitance and the greater the field produced at the input to the device, and the faster the device turns on and off. However, a problem can arise if the oxide is too thin; the oxide can break down and effectively short the transistor. Another problem is the additional time it takes to charge the larger capacitance, given the same drive currents and drive impedance.

Yen Chang says typical oxide thickness for 0.8-µm processes are on the order of 170 Å. For 0.5-µm processes, the thickness is on the order of 135 Å. These thinner-gate oxide thicknesses require a lower voltage--hence the demand for 3.3 V at 0.5-µm process rules and below. Bhadrik Dalal says that gate oxide thickness reaches a theoretical limit at around 60 Å.

In the fast-paced semiconductor industry, developing a foundry relationship becomes increasingly important for designers who develop an IC in one process technology with the intention of migrating future versions of the design into smaller process technologies, says Zoran's Sinar. The problem is timing the completion of a new design with the availability of a new process technology.

Sinar cites the example of a Dolby AC3 Surround Sound chip that his company, Zoran, has begun shipping. First to market with the 0.6-µm chip, it will be in almost every digital video disk player announced in September of this year. However, the pressure for Zoran is to build the next generation of DVD multimedia chip in a 0.5-µm process before competitors steal the next-generation designs away.

How does a designer create a design for a nonexistent process technology? Sinar says Zoran's foundry, TSMC, creates Spice models of transistors for next-generation processes using an existing process. Sinar says that foundries such as TSMC have learned the importance of technology migration for their fabless customers. They are already developing models for 0.35-µm processes yet to come.

Early attempts at creating estimated Spice models were crude at best. However, over time, foundries have refined the techniques so that the predicted Spice models are now closer to the final process. Sinar says the Foundry User Network (FUN) was an ad hoc group that worked with foundries to validate models before they were released. FUN is now part of the Fabless Semiconductor Association, an industry trade group (Dallas, TX).

Figure 2. The diagram shows a cross section of the 2-input NAND gate in shown Figure 1. Illustration courtesy of Rubicad .

Another concern designers have in dealing with foundries is the variability of their Spice models. Typically, foundries provide nominal Spice model values. Cascade's Scoones says that using nominal values can lead to lower yields. If the manufacturing process drifts into its worse-case region, chips designed to nominal Spice values may fail to meet specification, thus, becoming scrap. Designers need to demand worse-case Spice values from foundries and they need to create their designs to these data.

Users speak out on silicon performance issues

Integrated System Design recently conducted an electronic survey in which some of our readers and the membership of the Users Society of Electronics Design Automation (USE/DA) were asked about their experiences with ASIC performance. From this survey, we concluded that the users are unhappy with the device and interconnect models and are starting to experience problems with performance related to interconnect parasitics. We also learned that simulation and synthesis tools are universal, but analysis tools for parasitic extraction, timing, and power are not that common. Few of the users are applying accelerators or emulators to the verification tasks. We also found that silicon performance varies due to physical construction and processing differences with the result that a design may not perform to specifications from vendor to vendor. In response to our questions on ASICs working and going into production, most of our respondents had successful silicon, and the working parts were either in or going into production. The parts that had problems, (except for complete failures) were used as-is in production. This response was unexpected because the ASIC vendors still feel that about half of the ASIC starts do not go into production. A number of the readers were working on mixed-signal designs where model accuracy and performance was critical to the success of the design. One user designed a micropower low-voltage analog design. The user stated that the vendor worked well both technically and commercially. A custom FPGA-based emulation system in conjunction with the requisite simulator and synthesis tools, coupled with careful power and timing analysis, contributed to the successful IC design. Soheyl Pourmehdi of NeuroControl Corp. (Cleveland, OH) and Case Western Reserve University (Cleveland, OH) is another successful mixed-signal designer. Pourmehdi responded that the models caused no problems, that the simulations and results matched in the mixed-signal design. When asked to pick if vendor-supplied design rules and models permitted maximum performance or if they were over guard banded, very few maximum performance responses were given. Most of the answers leaned towards over guard banded. Todd Shelton of Sorenson Image (Logan, UT) said the models he used gave maximum performance for the proof-of-concept prototype he built. He noted that although the parts will not go into production, the parts produced from his GDSII layout performed as expected. Shelton used simulation, synthesis, and timing analysis to achieve his first-pass working silicon. Simon Lau of Eureka Technology Inc. (Los Altos, CA) noted that most of the ASIC vendor's library was heavily guard banded. The actual silicon gate delay was much faster than the simulation's numbers--giving plenty of margin in setup time, at the expense of not enough margin at hold time. Lau noted that this type of approach is simply wrong because hold time is as important as setup time; it would be better for the ASIC vendor to put the same emphasis on both quantities. Eric Beuville of Lawrence Berkeley National Laboratories (Berkeley, CA) stated that models are getting bad for technologies smaller than 0.8-µm. He used both a BSIM 1.0 model and a level-28 model in HSpice and found the transconductance and output conductance parameters didn't match the silicon performance. He ran his design in multiple foundries through the MOSIS service and found a noticeable difference in the performance and circuit density. Yaw Fann of IDT Inc. (San Jose, CA) said that the models are not accurate but IDT did not have any problems in getting to working silicon. The timing analysis tools compensated for the model inaccuracies. Despite having access to a full suite of tools and overly guard banded models, a user at a major semiconductor company told us that he has to redesign the IC to correct timing problems associated with loading and routing. Excluding logic and other design errors, our respondents said that timing problems caused the greatest number of IC troubles. Other problems were (1) power consumption; (2) design process centering, a term describing the loss of functionality under processing corner conditions (parameters near process limits); and (3) boundary operating conditions, like high or low supplies and worse-case clocks. Imran Chaudhri of IgT Inc. (Gaithersburg, MD) took two passes to get working silicon, due to logic design and synthesis errors on the first attempt, and is planning to correct lingering design issues in the silicon on the next pass. Chaudhri is not sure if the models are accurate due, in part, to the logical problems, but is running the current design in limited production. The design was transferred in netlist format to the vendor for physical layout and routing. Another user at a major fabless semiconductor company said that he had difficulty with the interconnect resistivity causing problems with the timing in his design. He used an IKOS accelerator to verify his logic but did not describe any timing analysis tools as a part of his design flow. His GDSII layout had a 10 to 15 percent performance difference between two foundries that were both using a 0.6-µm process.

For designers in need of help to work through their first designs, a new class of service company is emerging that provides design implementation technology. The provided technologies include standard-cell and gate-array libraries as well as design services and tools to complete a design. Companies providing such capability include Aspec, Cascade , and Compass.

Part of the value-added services provided by these companies include cell libraries that are guaranteed to work at various foundries. Thus, if the designer creates a simulation that meets timing with a given library, the foundry guarantees working silicon, or it's their problem.

The trend for future designs implemented in deep submicron rules is for the designer to become more involved with chip layout. For the uninitiated, back-end layout presents a formidable barrier to entry. However, it's a barrier designers must overcome if their final circuit is to be competitive in the market.

Jonah McLeod is editor-in-chief of Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  August 1996