Design Automation

SPY vs. SPY: the VMC Story

How a past Cadence monopoly helped boost Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys and Viewlogic in today's IP market.

by John Cooley

Three years ago, while perusing the Internet's "comp.lang.verilog," I came across a posting from Cadence's legal department. It was a Cadence lawyer threatening to "take all available legal actions" against anyone who used or copied some recently posted program that somehow "violated" Cadence technology. He ended his post trolling for anyone to directly tell him anything related to this "violation."

I didn't know this Cadence lawyer, but my first impression told me he didn't fully understand human nature--or maybe he did, but was doing some sort of action required by law. Either way, by effectively posting "DON'T LOOK AT THIS FORBIDDEN PROGRAM," he suddenly got thousands of engineers now doing exactly what he didn't want--seeking out this forbidden program. (Isn't every college graduate required to take at least one course in basic psychology these days? Even God had problems trying to keep Adam and Eve away from the Tree of Knowledge.)

Later, I found something posted by "an33929@anon.penet.fi." This guy was using an anonymous re-mailer to hide his identity. How odd. A quick look yielded that he posted a Perl script which messed with the YACC debug code built into Cadence's Verilog-XL. Whoa! It cleverly tricked the debugger into unprotecting any Verilog that was encrypted using Cadence's proprietary encryption scheme! Whoa!

Many ASIC foundries were "encryption happy" during this period. They were encrypting stupid stuff like their simulation libraries--even though all this information was easily found in their data books! Motorola Inc. (Phoenix, AZ) and LSI Logic Corp. (Milpitas, CA) were famous for this, and, to add salt to the wound, most of their newer Verilog libraries weren't even debugged. As a customer, if you wanted to try to figure out why your simulation wasn't working and suspected the library, you were stuck because the damn libraries were encrypted. A Perl script that blew away this stupid encryption meant you could literally save weeks or months in quickly finding the bugs in the foundry's Verilog libraries. Otherwise, it meant a long, involved political process of begging and making animal sacrifices to the God-like rulers of the various petty kingdoms within Motorola or LSI Logic just to get them to check for possible bugs in their own libraries. It wasn't pretty.

Three years earlier, the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys legal department came after me for starting ESNUG. Since then, I've made it a policy to keep my computer free of anything that might attract lawyers. Therefore, no matter how enticing that illegal script was, I had to painfully leave it behind.

Because this script was so useful, some people suspected that it wasn't a user who created it, but rather an angry EDA vendor. Although Verilog had just become an "open language," Cadence Inc. (San Jose, CA) very cleverly made the encryption algorithm proprietary--thus keeping most customers locked into using Cadence's Verilog simulator because it was the only one around that could run those damned encrypted libraries. This angered most of the other EDA vendors on the OVI board, so when An33929 published his script, a lot of Cadence people were unofficially pointing fingers at such people as Chronologic's whiz kids Peter Eichenberger and Mike "Mac" McNamara as having the technical ability and the motive to do this. Also, since Cadence was consistently being embarrassed by Chronologic's extremely high-speed Verilog simulator, Cadence would have loved to have "just cause" to use the courts to shut down Chronologic Corp. (Los Altos, CA). As is the norm in the EDA world, this was just rumor-mongering. Nothing was ever proven.

Figure 1. Notice how "clock" is used in this sample VHDL prior to being KRYPTON-ized (these "before" and "after" examples were taken from LEDA's own web site).

The French connection While all the Verilog-supplying American EDA companies on the OVI board were caught up in the corporate equivalent of a "Three Stooges" food fight, on the other side of the Atlantic, in the VHDL world, a small French company called LEDA approached the encryption problem in a completely new way. Unlike Cadence, LEDA couldn't just create a proprietary encryption scheme and use their clout from having a huge share of the market to get everyone to use it. Instead, LEDA created a code scrambler called "KRYPTON," which they sold as an encrypter that could output universally executable VHDL.

KRYPTON is effectively a very clever Perl script that removes comments; removes indentations and spacings; renames all signals and variables to hard to read "I", "1", "0", and "O" strings; replaces constant declarations and static expressions by propagating their values; elaborates all sub-programs and removes unused sub-programs; and, whenever possible, uses VHDL's overloading rules to cleverly shuffle around subprograms (see Figure 1 and Figure 2).

A major advantage to KRYPTON-ized VHDL is that it can run in any VHDL simulator from any EDA vendor. Because it does some of the elaboration of the source VHDL, the KRYPTON-ized VHDL can actually compile faster.

A drawback to KRYPTON is that all the VHDL keywords are retained. Thus, if someone was really motivated, my guess is that they could put together a rough functional facsimile of the original source code if they worked it out carefully. For example, I found which signal was "clock" because of the WAIT ON keywords. Of course, if it involved a large file, piecing things together could take an awful lot of time--probably far longer than it took to write and debug the original source VHDL itself.

The other drawback is that KRYPTON output is rewrappable. It enables the unethical to steal and resell other people's designs. For example, suppose I bought a VHDL model of a Pentium processor that was scrambled with KRYPTON. Because it's all still simulatable VHDL, after a little editing I could just rerun that Pentium model through KRYPTON again to rescramble it a second time. Then I could resell this output as my original work. In contrast, the proprietary Cadence Verilog encryption algorithm's output can't be run back as an input, thus making rewrapping impossible.

Also, KRYPTON output isn't synthesizable, either.

Meanwhile, back at the ranch... Despite the encryption lock Cadence had in the American Verilog world, Chronologic was beginning to take a serious bite out of Cadence's Verilog market share with their faster compiled Verilog simulator VCS. In June 1993, EE Times reported a Verilog benchmark, done in the UK by David Wharton of DA Solutions, which found that Chronologic's VCS was 7.7-times faster than Cadence's TurboVerilog. Chronologic plastered print ads about this everywhere. If a customer was buying their first copy of VCS to replace a Cadence license, Chronologic sold it to them for $5,000 instead of their list price of $44,000. Chronologic even ran taunting anti-Cadence print ads showing a picture of what appeared to be Joe Costello's Jaguar (it had a California vanity license plate of "CDN1") over which was written, "We're Investing In Faster Verilog. They're Investing In, Well, Who Knows?" In a more recent benchmark that appeared in the March 1995 issue of Integrated System Design, Yatin Trivedi and Larry Saunders of Seva Technologies (Fremont, CA) still rated Chronologic's VCS as being twice as fast as the upgraded Verilog-XL.

It was in this atmosphere that Chronologic's Eichenberger brainstormed a clever way around Cadence's lock in the Verilog encryption market. It was a new product called VMC--Verilog Model Compiler. Essentially, VMC takes advantage of the fact that Verilog's PLI can execute object code. When a design is digested by VMC, it is first compiled from Verilog to C. Then the C version is optimized and compiled to object code. Internal wire, register, and module names are either destroyed or rehashed to humanly unintelligible garbage. Thus, even a clever hacker using the Unix "strings" command on the object code can't get any forbidden insights. The person encrypting with VMC can also choose non-port parts of a design (like certain internal registers in a model of a 486, for example) to be visible to the model user.

Figure 2. Notice how the keywords "WAIT ON" show which signal is "clock." I contend these remaning VHDL keywords provide enough clues for an engineer to piece together what the scrambled VHDL does.

Overall, VMC output has the interesting property of being encrypted, yet executable, in any Verilog simulator that supports the PLI (Cadence, Mentor/ Model Tech, Frontline, Fintronic, VeriBest to name a few). An ironic side effect of using VMC-encrypted models is that it offers "free" acceleration to end-users of the models. For example, if you used a VMC-encrypted model of a MIPS processor in a Cadence Verilog simulator, because the model was accelerated by Chronologic, it will run faster than if you had the MIPS processor Verilog source code itself running in the Cadence simulator! This "free" speed-up only comes with RTL or behavioral Verilog. Gate-level Verilog netlists aren't accelerated by VMC.

One of the sexier appeals VMC has for IP model developers is that, because it uses the Verilog PLI, designs can't be "double wrapped" (they could be double wrapped using LEDA's KRYPTON). This means it blocks the repackaging of other people's designs. You can't even VMC-encrypt a design that uses any VMC-encrypted subdesign anywhere in its hierarchy. You can always run hierarchical designs using VMC-encrypted parts--you just can't re-encrypt them.

Table 1
The four current ways of encrypting designs
	Cadence Verilog encryption	LEDA KRYPTON	Chronologic Verilog Model Compiler (VMC)	Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys DesignWare
Language(s)	Cadence Verilog only	All VHDL '87 & '93 simulators	Reads Verilog: runs on all Verilog and VHDL, plus others	Mostly VHDL: some Verilog
Simulatable?	Yes, but only on Cadence	Yes, universally	Yes, universally	No, only in netlist form
Synthesizable?	No	No	No	Yes
Accelerated?	No	No	Yes	No
Secure?	Hacked only once	Not 100%; keywords are great clues	Very secure; never hacked	Very "iffy"; netlists show design
Limits?	Can handle large & small designs and ASIC libraries	Better with big designs. No netlists. No ASIC libraries	No speed up on netlists. Likes bigger designs. No ASIC libraries	Big netlists are more "secure"
Rewrappable?	No	Yes	No	Yes, but only on specific netlists

Table 1. It's a little unfair to put DesignWare in with IP encryption techniques because it's more of a synthesis building block scheme. For protecting models, currently VMC is the most secure and universally executable approach so far.

The minor drawbacks of VMC are that encrypted models aren't capable of being synthesized or annotated. Because one could use the PLI procedures that are used for backannotating timing delays into Verilog netlists to pluck out all the wires, registers, and other objects in the encrypted Verilog model, VMC supports only a very limited subset of the PLI. Hence, VMC-encrypted designs can't be annotated, but I'm told they're working on a way around this for future revs.

All quiet on the western front What's a good EDA brushwar without Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Inc. (Mountain View, CA)? Although Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys offers DesignWare, a way to make synthesizable parts that Design Compiler can use to make ASICs, DesignWare is not simulatable until after synthesis. It's the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Logic Modeling group that separately offers customers the 14,000 simulatable models.

Once word got out that Chronologic had VMC, it became very obvious that the major ASIC foundries working on lots of IP cores (like LSI Logic) could suddenly now become large-scale independent distributors of models and designs. Why go to the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Logic Modeling group for a model of an AMD29000 when VMC enables AMD to securely give you the model themselves? "We used VMC to encrypt our CW4001-3 MIPS RISC processor cores," said Darren Jones of LSI Logic, "It worked perfectly."

In early January 1995, Viewlogic's stock suddenly dropped 50 percent. This triggered an attempted corporate divorce between Chronologic and Viewlogic that resulted in much of Chronologic's R&D staff leaving. As a result, VMC was delayed by about eight months as a new R&D staff took ownership.

Getting the new VMC R&D staff in place was the only thing blocking the new Chrono/Viewlogic from making untold millions in the burgeoning IP market, right? Wrong.

"Semiconductor vendors don't want to take calls from EDA users when their third rev of a 68360 QUICC model isn't working with their Model Tech VSIM 4.2 on SUN O/S 4.1.3," said David Hardman, general manager of Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys ' Logic Modeling group (Beaverton, OR). "Encrypting is only one part of the IP business. There are massive distribution and support problems to overcome that Chrono isn't interested in."

Thus, Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys and the new Chrono/Viewlogic entered into a marriage of convenience in the IP business, where Chrono/Viewlogic provided VMC and Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys provided their SWIFT interface, models, and end-user support.

The big win for Chrono/Viewlogic was attaining access to the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys proprietary SWIFT interface. SWIFT enables VMC to run encrypted Verilog models on both Verilog and now VHDL simulators, plus many other esoteric simulators like IBM's AUSSIM, VEDA's SysHILO, and Mentor's QuickSim II.

The big win for the Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Logic Modeling group is that VMC effectively cuts their six to 12 month engineering schedules down to a few weeks for each new model. To make secure models via their proprietary LADL environment, Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys would either have to recreate designs from specs to LADL or translate designs from Verilog/VHDL source to LADL. From LADL, it was then converted to C binary for customer use. "For NEC, it took us eight man-months to build a bus-functional model of the R4300 MIPS processor from specs and test vector," said David Hardman. "On a PowerPC 401 model for IBM, since IBM used VMC, it took us only six weeks; and that was mostly hand implementing and re-validating the SWIFT interface. Once VMC has SWIFT implemented, this will be automatic."

The big win for the semi houses and other IP creators is that with VMC, they no longer have to nervously give anyone Verilog/VHDL source code and then pray that the NDA is always honored (see Table 1). Also, the greatly reduced time it takes to make models secure for customer use directly translates into more time available to make more models for customers. Overall, VMC seems to be a winning product for everyone involved--except Cadence.

What goes around, comes around As any student of military history can tell you, secrets have expiration dates. That is, given enough time, effort, and motivation, even the most complex of cyphers have been broken. EDA encryption schemes promise to be no different. They function purely because it takes far more work to crack them versus making the design on your own.

When Ewald Detjens was still the CEO of Exemplar Logic Inc. (Berkeley, CA), I used to enjoy hearing his outspoken views on panels at EDA conferences. When someone tried to garner sympathy for those who got "hurt" by Cadence's encryption being broken (namely, Cadence and the semiconductor houses), he replied, "Aw, Hell, these guys spy on each other all the time! They constantly take each other's chips apart. There was nothing they've encrypted that isn't already known in intricate detail by their competitors."

Cadence keeping its encryption scheme proprietary gave them a temporary advantage in the Verilog market. Ironically, this lack of cooperation on Cadence's part is also what spurred Chronologic to make VMC in the first place. It later contributed to the partnership between Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys ' Logic Modeling and Chronologic--giving them both a better position over Cadence in the growing models and Intellectual Property businesses. I wonder how this would have changed if Cadence had instead cooperatively created a universal encryption scheme when it opened Verilog?

John Cooley moderates the grassroots E-mail Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Users Group (ESNUG) and is a contract ASIC designer. He loves e-mail from fellow engineers at "jcooley@world.std.com" or call (508) 429-4357.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@isdmag.com.

integrated system design  December 1996