EDA Platform

IC Reliability Keeps
Deep Submicron Out
of Deep Doo-Doo

Steve--whose vocabulary has obviously been affected by the rearing of his toddler--explains why you should expect EDA tools to become a necessary part of every IC designer's toolbox.

by Steven E. Schulz

If you're an IC designer in today's booming market, then odds are you're being asked to design more than ever before, in less time, with circuits that take full advantage of newer processes. With so much design pressure on greater functionality and performance, it's difficult to even think about squeezing-in additional design constraints that are, at best, a nuisance. Although IC reliability is often an afterthought to functional design, the trends of deep submicron are now pushing it up-front as a concurrent design tradeoff (with everything else). The fact is, to coax reliable performance out of ridiculously small geometries, device physics now plays a critical role in determining feasible design choices. EDA tools are slowly rising to the challenge, but over the next few years expect them to become a necessary part of any IC designer's toolbox.

Design-for-reliability can be defined as assurance that a circuit will continue to function within spec, across all allowed process variations and environmental conditions, for its full rated lifetime. The major issues today are electromigration (EM), electrostatic discharge (ESD), electrical overstress (EOS), latchup, antenna effects, and hot electrons. In the following paragraphs, I'll summarize each one--what designers can do about it, and how EDA tools can help.

EM is the migration of metal atoms along the path of current flow in an IC. It occurs when the current density exceeds safe limits for a long enough period of time. EM, most frequently found in power and ground rails, is characterized by relatively large amounts of current flowing in a single direction. To avoid EM failure, it is necessary to know the width of the deposited metal (assuming constant thickness), the power consumed by all active and passive devices, and how the current flow is distributed to those devices. EDA tools exist that can extract line widths from the layout (correlated with the electrical view), generate an equivalent RC network, run power simulations of the design with input vectors, and calculate current densities over time. It is also possible to predict the EM lifetime of the device from these simulations.

ESD is a well-known effect in which electrostatic voltages are applied to the I/O pins of an IC during human or machine handling. These voltages typically range in the thousands, so I/O cell protection is tricky business in submicron technologies. If 5V circuit designs weren't difficult enough, the trends for shrinking CMOS voltages and higher densities make protection an even greater necessity. The solution is to insert special ESD circuits attached to I/O cells, designed to reroute high voltages away from internal circuitry. Once a design has completed layout, EDA tools can check to see if the right ESD circuit has been used for a given class of I/O cell, and if it meets certain minimum dimensions. Device/process simulators may also be helpful in designing ESD circuits, and research is under way that may someday help predict ESD performance of designs for new processes.

EOS is similar to ESD, except that the time duration of the failure mechanism is longer, while the voltages are less. As with ESD, device damage is prevented by adhering to certain very specific minimum feature spacings in layout and other tricks. EDA tools can validate adherence to these spacing rules from a layout database.

CMOS latch-up occurs when the n and p diffusion regions that make up a CMOS transistor are close enough in proximity to act as a parasitic bipolar SCR device. If the loop gain exceeds unity, then the SCR can trigger, generating large damaging currents. Latch-up is avoided by guard rings and/or minimum spacing rules. An EDA tool can check for adherence to these rules from layout.

Antenna problems are a side-effect of the manufacturing process. Plasma etchers or ion implanters induce a voltage into isolated leads, overstressing thin gate oxides. The leads (polysilicon or metal) act like an antenna when the ratio of poly-over-field (thick oxide) to poly-over-gate (thin oxide) is too large. As the oxides of new processes get thinner, the problem becomes proportionally worse. Designers can avoid this by ensuring the layout ratios are within set limits or by adding devices to each gate. Once again, EDA tools can check for adherence to these rules from layout.

Hot electrons are a degenerative problem that occur when strong electric fields energize electrons sufficiently to mobilize into the gate oxide and cause permanent shifts in threshold voltage, reducing drive current capability. Normally, careful process design should all but eliminate this as a design issue, but special SPICE models fitted to measured parameters can help predict potential hot electron degradation effects in either analog or digital designs.

While the relative priority of the issues above is highly application-dependent, general industry trends suggest that EM may be the greatest overall concern. That is not to say that it is the most common; ESD/EOS failures occur far more frequently. Yet, the inability to test for expected EM lifetime, coupled with its tendency to fail long after being installed, makes it a literal time bomb in the customer's hands. Not long ago, Maxtor (San Jose, CA) filed a multimillion dollar lawsuit against Zilog (Campbell, CA) for EM failures on parts that had been in service up to four years! This not only hurts financially, but also takes a toll on company image and market share. Fortunately, these risks can be controlled with the help of design automation. Most solutions are still based on internal foundry tools, although some companies, such as Epic Design (Sunnyvale, CA) now offer commercial solutions.

It's tough enough to "design in" everything that a VLSI chip should do, without also having to "design in" what the chip shouldn't do. But as we squeeze the maximum performance from every molecule of silicon and aluminum, it's a business reality that simply cannot be ignored. The EDA industry will need to respond. *

Contributing editor Steven E. Schulz, P.E., is a member of the technical staff at Texas Instruments (Dallas, TX).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  March 1996