EDA Platform

Synthesis Standards
Are Key to Design Reuse

Design reuse will require more changes in methodology and industry cooperation.

  by Steven E. Schulz

In the spirit of election year, I'd like to borrow a chapter from page one of our US political system and proudly announce that I strongly favor design reuse. We should do more of it. Reuse of existing designs will keep our fabs full, sustain our economy, and save us from that ghastly "productivity bottleneck." I just have one question: what are we waiting for?

The vision of design reuse is centered around recognizing the rapidly growing value-added of intellectual property (IP) in the semiconductor industry. It can be shared within a company, in mix and match style, or licensed to some other company or companies. IP is rarely a commodity; it maintains high margins through differentiation. There's lots of money to be made in owning it, sharing it, and enabling access to it. What was once a foundry is now a "solutions provider." What was once a design is now a knowledge base (and ongoing revenue stream).

Design reuse is critical to the future growth of the electronics industry; yet, very few companies have put in place the necessary standardization and infrastructure to tap their own knowledge base effectively. Reuse occurs today but only in special cases and only by brute force. Reuse is even less common between companies. In general, today's automation environments don't do much to help designers leverage pre-existing IP.

Re-implementing a design requires understanding the original design's intent. In today's world of synthesis-driven flows, design intent means more than just HDL code. VHDL or Verilog designs necessarily include numerous in-line synthesis directives called "pragmas." Such directives are not optional; they are needed to fill the gaps in the HDL description for implementation in hardware. Just as importantly, once a design has been released, the source code (HDL plus directives) serve as official, unambiguous documentation for that design, which is necessary for detailed understanding.

Last year, VHDL International's board of directors challenged the VI Technical Advisory Committee (TAC) to seek out the "next VHDL initiative towards ASIC libraries (VITAL)"--that is, to pro-actively identify the next barrier to customer productivity and begin a technical effort to resolve it. The VI TAC selected synthesis interoperability and has recently transferred ownership of this issue to the EDA Industry Council--official sponsor of the EDA Standards Roadmap document. A new "RTL Subset Project" is currently ramping up with Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys ' active participation.

OK, so what must be standardized--just an RTL subset, right? Wrong. The RTL subset is only one piece of the puzzle. Full interoperability requires standardizing (1) RTL semantics and constructs, (2) synthesis constraints (directives and constraint files), and (3) libraries. I will concede, however, that library interoperability has more impact for ASIC and FPGA suppliers today than most users, and I will also concede that sharing "constraint files" used by synthesis tools are less important than in-line directives. Fortunately, VHDL designers now have a standard synthesis interpretation for the standard MVL9 logic system (including sensitivity to edge transitions) and signed/unsigned operators recently passed as IEEE standard 1076.3.

The description of design intent is contained not only in the RTL code, but also in the synthesis directives, which are themselves scattered throughout your source code. Is this really what you, as the customer, want to archive and depend on for reuse? Can you recreate a new IC chip from this description without them? Will other design teams understand these "pragmas," or do they use some other set? What if you need to retarget from an ASIC to FPGA or to another vendor tool? The solution is, once again, shared semantics and constructs.

The third piece of the puzzle is the synthesis library. There is some momentum building in the industry to extend the popular VITAL standard (for portable sign-off ASIC simulation libraries) to support synthesis as well. Is this the best approach? What are all of the tradeoffs? Technically, this could be a rather straightforward extension, but major business and marketing issues remain. Whether leveraging VITAL or some other means to achieve this goal, the newly formed Industry Council synthesis working group should address these issues in a bipartisan approach. Since any synthesis standard for libraries would occur at the source level, such libraries could still be portable and yet remain efficient after being compiled to existing vendor formats.

VHDL's flexibility and modularity through add-on "packages" made the early development and prototyping of VITAL--before committing to a paper standard--possible. This feature is important, because it has been argued that synthesis standardization would delay progress. However, this need not be the case. In fact, the use of the "package" concept could be the smoothest means for the syntax and semantics describing a new capability to be introduced to the market and then, later, added into the standard.

To support design reuse, customers should demand that the industry standardize on in-line synthesis directives along with the " Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys RTL Subset." For ASIC suppliers, the need for a synthesis library standard has been important for years. Similarly, ASIC suppliers should begin work on standardizing a synthesis library standard.

Let your voice be heard. I encourage you to send your comments to me at ses@dadd.ti.com. I have agreed to forward all responses to Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys so that they may assess whether there is a substantial customer need for standardization beyond the "RTL subset."

Synthesis has emerged as a critical path element for interoperability and reuse. If you truly favor design reuse and synthesis interoperability, let's stop the rhetoric. Let your EDA vendors know the time has come for change. After all, it's an election year.

Contributing editor Steven E. Schulz, P.E., is a member of the technical staff at Texas Instruments (Dallas, TX).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  May 1996