EDA Platform

A New HDL Environment In between Olympic events, Steve, sitting on his couch in his new home, outlined his thoughts of a new and revolutionary HDL environment. by Steven E. Schulz

How do you feel about change? Do you see it as a potential opportunity, or do you view change as more of a threat? It might seem that electronics designers would embrace change since they are responsible for fueling the electronic revolution of our modern world. But odds are some readers of this column will respond apprehensively to what I have to say in the following paragraphs. Let's see how you react.

The current state-of-the-art in HDLs is viewed by many across the industry as being insufficient for the upcoming challenge of "systems-on-silicon" design flows. Both popular HDLs (VHDL and Verilog) were defined in the mid-eighties with discrete event-simulation semantics; yet, since that time, the need for description of design intent has changed substantially. While today's HDLs have recognized limitations, trends hint that this problem will become far worse and will, in fact, become a major bottleneck to future growth of the semiconductor and system electronics industries.

Both VHDL and Verilog lack a number of features required to overcome the design and verification challenges universally referred to as the "design gap":

• Support for higher abstraction (notably the abstraction of time).
• Consistent, portable interpretation of design intent by EDA tools (RTL level and above).
• Formal semantics for use at higher abstraction levels by formal verification methods.
• Comprehensive description of design constraints and assertions.
• Clean separation of design intent from implementation specifics.
• Mixed-signal (digital, analog, RF) and mixed hardware-software functional description.
• Semantic support for mixed text/graphics design-entry styles.
• Ability to describe test, packaging, signal integrity intent/constraints.
• Ability to describe data flow architectures, loosely interacting processes.

Features such as these are key to effective design reuse in the future--a key goal of any system design capability. The SIA's National Technology Roadmap for Semiconductors documents general capabilities needed over the next 10-15 years in design and test, and the EDA Industry Standards Roadmap (sponsored by the EDA Industry Council) identifies areas where EDA standards can specifically enable those required capabilities from the SIA roadmap. This past June, the Industry Council approved key projects in synthesis standardization, system-level design, and reuse. Those projects are being coordinated by an inter-organizational technical advisory board (PTAB) reporting to the Industry Council.

This newly formed PTAB comprises 18 international appointees and representatives from the major standards development and approval bodies worldwide, including CFI, ECSI, EDAC, EIA, EIA-J, IEC-TC93, IEEE-DASC, OVI, and VI. The PTAB's charter is to provide technical direction and guidance to Council-endorsed standards efforts, and facilitate industry collaboration of existing groups working on development of standards which support the EDA Standards Roadmap. Gary Panzer of Hughes Aircraft was elected vice-chair, and I am honored to have been elected PTAB Chair.

Where existing technical groups are already at work, those efforts can become candidate standards for PTAB endorsement. But what about new areas where no standards group exists, such as in system-level design? This is an excellent opportunity for EDA standards to accelerate new design capabilities, although such widespread change requires equally widespread support.

A workshop on the topic of system level design (SLD) is being held October 1st-2nd in Dallas, Texas. The event, sponsored by the EDA Industry Council and hosted by Texas Instruments, will serve as the kickoff event for a new PTAB project on system-level design. The purpose is to develop general industry-wide consensus on the key problems facing the design of silicon-based systems, and to arrive at a consensus view on how these problems should be addressed through coordinated industry standards development. A worldwide group of experts from industry and academia have been invited to explore the possibilities, including recommendations in terms of scope, general approach, vision of the solution, development roadmap, and consensus on whether or not sufficient interest exists to proceed at this time. Soon after you read this column, the SLD workshop results should be available on the Web, under the Industry Council home page (http://www.cfi.org/ic).

Now, I know what some of you are thinking: "Steve, I can't believe you (of all people) are proposing a new HDL environment!" After all, I've been a loyal user and proponent of VHDL, already known for its (relatively) strong system-level capabilities. Both VHDL and Verilog will thrive on momentum for many years and should evolve to fill market needs. Yet, I foresee challenges we must face within the next eight to 10 years that will far exceed what can be fixed using the confines of our present HDL semantics. This may also be our best opportunity to unify the Verilog and VHDL communities with a long-term solution that incorporates the best of both worlds, hopefully satisfying both sides.

So, how did you react? If you are displeased by such radical proposals for change, I'd like you to consider what it will take to actually design and verify 50-million transistor ICs in the year 2007. On the other hand, if you can get excited over the possibilities, then I'd like to hear from you. e-mail me at ses@dadd.ti.com . In the coming months, I'll be reporting on the progress of the PTAB projects, including status of the synthesis standardization thrust, as well as results of the system-level design workshop. So stay tuned to this column for regular updates.

The "systems-on-a-chip" era has arrived, and it's time to start thinking about change for more powerful, portable, and complete descriptive capabilities in our HDL environment. Imagine the possibilities.

Contributing editor Steven E. Schulz, P.E., is a senior member of the technical staff at Texas Instruments (Dallas, TX).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  October 1996