EDA Platform

IP In HDL Using EDA for IC Acronyms abound, as Steve introduces us to a new industry alliance that addresses the role of intellectual property in design reuse. by Steven E. Schulz

With the recently announced Virtual Socket Interface (VSI) Alliance, the electronics industry has officially awakened to the critical role of intellectual property (IP) in design reuse. Although some of the companies that are members of the alliance are strong competitors in the semiconductor marketplace, they realize the need to work together to solve a new problem that could otherwise derail the projected growth rates of the entire electronics industry. The VSI Alliance appears to be a genuine business approach to a genuine business problem.

The VSI Alliance is built on the notion that EDA standards are necessary for tool and IP interaction. The design community has an insatiable thirst for more transistors and higher clock rates, but only if they can mix and match core functions from the best sources. The strange irony is that, in order for IP providers to leverage from proprietary technology, open standards are needed to an even greater degree.

It's interesting to note that some VSI Alliance members are presently--shall we say--"IP challenged." Many Far-East IC companies developed the sudden urge to quickly locate some IP following the 70 percent rock slide in memory prices. Consequently, they came to view this new alliance as a great opportunity to become "IP consumers."

There are actually two types of IP: the design data itself, as well as the manner in which that design data is formatted and processed by EDA tools. The data formats generally belong to the EDA suppliers and not to the customers. One might argue, "Wait a minute Steve, we use an IEEE standard HDL at our company, and that definitely isn't the EDA vendor's IP." Recall, however, that both languages were designed for event simulation, not synthesis or other validation algorithms (cycle-based, formal verification, emulation, etc.). Thus, one effect of the "synthesis revolution" over the years has been a subtle but important shift in whose formats and conventions are being adopted to describe IP and who owns the rights to those formats.

This may all sound fairly academic, but it should hit home within your design environment. Today, almost all EDA design flows depend on standards developed by working groups in IEEE, OVI, VI, EIA, and CFI, to name a few. As more complex combinations of design applications, EDA algorithms, and design methodologies are represented in EDA tool flows, so too will standards become far more prevalent as technology enablers.

Standards working groups must navigate around proprietary EDA supplier IP that exists in copyright form. Copyrights protect printed matter that applies to documented file formats for design data.

Yet a potential challenge to EDA standards groups has surfaced in the form of patents. Unlike copyrights, patents have deeper roots that protect fundamental concepts and methods.

One key example is a recent patent awarded to Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys for methods of converting an HDL description into a logic network. The Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys patent includes latch inferencing (for instance, how to assign HDL functionality between clock edges). Functional validation of RTL or behavioral HDL designs requires a consistent interpretation of HDL scheduling across multiple tools. This is of primary importance to most HDL designers worldwide. EDA patents such as these add an interesting wrinkle to the future of standards.

A new source of competition to design IP suppliers is arising from a familiar source--your friendly EDA suppliers. This should come as no surprise, as EDA companies interact with their customer's IP every day of the week, and have taken notice of the recent 30 percent growth rates of the IC industry (compared to their own 18 percent industry rate). These new fabless warriors are emerging from the major EDA companies with pleasant names like "consulting services" and "technology partners." The value proposition of staffing up this form of "consulting" at the expense of new product development is hard for some EDA executives to resist.

What are the consequences? It is probably too early to tell, but in some cases the practice of bundling new tool technologies with service contracts has caused a lot of hard feelings with customers. Many experts believe some leading-edge EDA products have missed market windows as a result of this bundling, and rumors abound of customer companies tightening down the hatch to ensure their IP is well protected from on-site application engineers.

To be fair, these EDA companies certainly have an equal right to play in the IP ball game. But we need to be aware of the potential hazards associated with their involvement, as well. Many leading-edge semiconductor houses are becoming increasingly concerned over the growing gap in EDA tool capability. Thus, new algorithms will require more in-house development to retain leading-edge capability.

Several years ago, Dell Computer Corp. (Austin, TX) filed a patent lawsuit against other PC makers who were using the VESA communications bus standard, claiming that the VESA bus was their intellectual property. The court ruled that Dell's failure to disclose their technology during the VESA standards development process played a key role in the decision to reject the suit. The court also noted the serious damage that would have been incurred to the growth of the PC industry if the VESA bus had fallen victim to the Dell claim.

This story is analogous to our own EDA industry, where our HDLs serve as the critical "communications bus" in today's design flows. Everyone (but the lawyers) will be hurt if copyrights and patents are not resolved to allow standardization of our design description formats.

Contributing editor Steven E. Schulz, P.E., is a senior member of the technical staff at Texas Instruments (Dallas, TX).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  December 1996