Editorial

Time to Change the Metric For Measuring IC Feature Sizes

Metal pitch, not gate length, is a more accurate indicator of die size in deep submicron ICs.

by Jonah McLeod

The ultimate determiner of worth for a semiconductor manufacturer is the size of the final die his process produces. The smaller the die, the more cost-effective the manufacturing process. However, integrated circuit manufacturers define their production process in terms of component feature sizes, typically gate lengths.

Bob Payne, chief technology officer at VLSI Technology Inc. (San Jose, CA) has a problem with this current practice. Most IC vendors claim to offer fine-line process capability using the Leff gate lengths to calculate the figure.

Payne contends, as process technology has reduced feature sizes below 0.5 µm, gate lengths no longer accurately predict packing density of gates per given area of silicon. While most of Payne's competitors will argue that he is biased, other more authoritative voices are echoing his contention.

Figure 1. A fully-contacted metal pitch (via-on-via) aligns all the vias on a grid so that metal pitch is the width of, and spacing between, any two vias. Line-on-via spacing permits tighter spacing by staggering the via. Thus, metal pitch is the width of the via plus the spacing between via and adjacent line.

One dissenter making the same argument is Professor Chenming Hu of the University of California, Berkeley. He made his case at the 1994 Integrated Solid State Circuits Conference in San Francisco, CA. Hu says the classical MOSFET model overstates the benefits of gate-length reduction. "Discussions of device scaling are often based on simplistic device models. Much more accurate models have become available recently but remain largely unknown to the circuit and design communities."

Payne contends that metal pitch--how closely the metal lines that route signals from gate to gate can be placed together--more accurately determines die size than does gate length. Metal pitch consists of two parts--the width of the metal line and the minimum amount of space needed to separate one line from another.

In addition, metal pitch is affected by how the IC manufacturer aligns the vias on metal lines. In a layout, the via is a square laid atop a metal line and spilling over both sides of the line equally (Figure 1).

Typical cell-based designs employ coordinated design rules, Payne asserts. Under these rules, transistor layout design coordinates with metal pitch. Furthermore, metal pitch sets the spacing between drain contact to source contact in a transistor. It also sets the spacing from drain to drain of isolated transistors. Libraries are based on multiples of fully-contacted metal pitch, Payne says. Thus, pitch determines cell dimensions and library elements shrink with pitch.

Payne recommends a change in the metric, specifying ICs implemented in process rules below 0.5 µm. We believe his suggestion warrants consideration. *

Jonah McLeod is editor-in-chief of Integrated System Design.

integrated system design  February 1996