Editorial

Can Synopsys Redefine Design Methodology Again?

Addressing timing and architectural variables in synthesis.

by Jonah McLeod

Critical paths failing timing specifications and evaluating alternative system architectures before committing a design to synthesis are two major problems for deep submicron IC designers. This month, Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Inc. (Mountain View, CA) debuted Behavioral Compiler--a product that Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys claims will solve both problems.

To understand the uniqueness of the new tool requires a description of the problem. In deep submicron designs of 0.5µm feature sizes or less, the delay in the interconnect exceeds the delay through the gates. Thus, estimated timing values in synthesis design libraries, which integrated circuit vendors provide to designers, are insufficient to ensure correct timing. The libraries only contain estimates of timing delays through gates containing various amounts of output fanout.

Designers must floorplan deep submicron designs after synthesis to acquire more accurate estimates of wiring delays. A floorplanning tool creates a layout of the major blocks and the gates within the blocks of a design. It then extracts timing delays along wires connecting individual gates and those running between blocks in the layout. It back annotates the delays to the synthesis tool.

Once the synthesis tool receives the backannotated delays, if the design contains too many timing errors, the designer may resynthesize the entire design and create a new floorplan. The problem is that he may create as many timing errors in the second iteration as in the first.

The other option is not to resynthesize the design but to resize the drivers along each failing critical path. Deep submicron designs typically have too many defective paths for this technique to be effective. Behavioral Compiler attacks this problem by selectively retiming critical paths that do not meet timing. Today's synthesized logic consists of groups of combinatorial logic separated by register elements. The amount of logic in front of or behind register element boundaries is adjustable. In failing critical paths, the new tools move combinatorial logic relative to register elements to achieve a timing specification.

Together with driver resizing, Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys claims behavioral retiming can fix failing critical paths with far fewer iterations between floorplanning and synthesis than heretofore possible. However, this is only one strength of the new tools.

A more significant feature is architectural exploration. Time-to-market pressure permits little design exploration before committing a description to gates. On new designs, after the designer creates a behavioral specification, he can construct multiple architectures from the one specification. The new tool maps designs into an architecture comprised of a datapath, memory, I/O, and a finite state machine controller.

Thus, the designer can analyze combinations of technology to specific datapath and memory resources. He can trade-off throughput and latency using high-level constraints. Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys cites several examples of designs completed using a conventional RTL methodology versus Behavioral Compiler. A 17,000-gate ATM cell Scheduler that took six weeks with the former was done in two weeks and 14,000 gates with the latter.

If design engineers achieve the results that Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys claims, the new Behavioral Compiler could be bigger than any product the company has launched.

Jonah McLeod is editor-in-chief of Integrated System Design.

integrated system design  April 1996