Editorial

Can the Rambus DRAM
Finally Emerge as a Mainstream Memory Chip?

Higher processor speeds will require faster memories

   by Jonah McLeod

Clock rates for Pentium and clone microprocessors are rising at a rapid rate. In February Intel Corp. (Santa Clara, CA) announced a 200MHz Pentium to ship in the fourth quarter. Furthermore, writing in the March 1996 edition of Microprocessor Reports, Linley Gwennap predicts a 233MHz P6 CPU for shipment in the first half of 1997 and a 333MHz P6 CPU by the second half.

One result of higher CPU clock speeds is the demand for higher speed buses. Today, CPU bus speeds of 66MHz are common. With faster CPU clocks, future generation systems will eventually achieve full 133MHz PCI bus speeds. Such high-performance buses will demand much faster DRAM memory.

Gerd Schauss, product marketing manager for memory products at NEC Electronics Inc. (Mountain View, CA) says most PC system manufacturers have already shifted production from fast page-mode memory to extended data-out (EDO) DRAMs. The prevailing view is that EDO is sufficient for the current generation of systems running 66MHz bus speeds.

Schauss expects bus speeds of 100MHz and over will require higher performance synchronous DRAM. He says SDRAM shipments will increase mid-year driven by the chip's faster performance and a reduction in price. SDRAM's performance will be fully realized when chip set vendors build components that use the memory's unique characteristics.

A perennial contender to replace conventional DRAM and now SDRAMs in main memory is the RDRAM from Rambus Inc., (Mountain View, CA). Subodh Toprani, vice-president of marketing, at Rambus says the RDRAM offers a significant speed advantage over SDRAMs. The company just debuted a 600MHz speed-grade version of the 16Mbit chip. SDRAMs run at clock speeds around 100MHz.

In addition, the RDRAM has a feature compatible with the P6 microprocessor coming from Intel next year. The processor can perform up to four memory accesses concurrently. For example, it can write to two locations at the same time it reads two other locations.

Toprani says a typical P6 system will contain two or more 64Mbit DRAMs--a minimum of 16Mbytes. Two SDRAMs will afford the P6 only two concurrent operations. By contrast, an RDRAM contains two separate memory banks, allowing two concurrent operations per chip. Thus, in a two chip system, the RDRAM accommodates four concurrent memory accesses.

Combined with the 600MHz clock speed, the RDRAM makes a compelling case against other alternatives. The argument was persuasive enough for Nintendo Co. Ltd. (Kyoto, Japan). The video game maker's new Ultra 64 system contains two RDRAMs.

For the Rambus memory to serve in main memory hinges first on cost and secondly, on market acceptance. The memory is now 10 percent larger than competitive devices because of the control electronics it contains. Implemented in a 0.25µm processes, the control electronics overhead is a more acceptable 3 percent.

The more overriding factor is Intel and the larger group of PC manufacturers. Choosing SDRAMs, they are assured of supply from every DRAM maker worldwide. Choosing the RDRAM limits the supply to only DRAM makers with RDRAM licenses from Rambus.

Jonah McLeod is editor-in-chief of Integrated System Design.

integrated system design  May 1996